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US 7,924,596 B2Granted
Area efficient programmable read only memory (PROM) array
AssigneeIntel Corporation
InventorsZhanping Chen, Kevin Zhang
Life of this patent
Estimating the term…
Abstract
A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row.
Claims21
A programmable ROM (PROM), comprising:
- an array of fuse cells, wherein a fuse cell includes first and second cascode NMOS transistors connected to a programmable fuse;
- a bit line connecting the fuse cell to other fuse cells in a column of the array of fuse cells;
- and
- a sleep PMOS transistor connected to the bit line that in a standby mode of the PROM shut off the fuse cells in the column of the array.
1 more element
A programmable ROM, comprising:
- fuse cells connected in a column by a bit line, wherein a fuse cell includes a first NMOS transistor and a second NMOS transistor serially connected to a programmable fuse;
- and
- a sleep PMOS transistor connected to the bit line that in a standby mode of the PROM shut off the fuse cells in the column of the array.
A programmable ROM (PROM), comprising:
- an array of fuse cells, wherein a fuse cell includes first and second cascode transistors connected to a programmable fuse;
- a row decoder to supply a row select signal to a gate of the first cascade transistor and a program control signal to a gate of the second cascode transistor;
- a bit line to connect the programmable fuse to other fuse cells in a column of the array of fuse cells;
- a line to commonly connect source terminals of the first cascade transistor in a column of the array of fuse cells;
- and
- a sleep PMOS transistor connected to the bit line that in a standby mode of the PROM shut off the fuse cells in the column of the array.
3 more elements
Dependencies are inferred from the claim text.