Semiconductor memory device having improved voltage transmission path and driving method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsSun-Won Kang, Seung-Duk Baek
Life of this patent
Estimating the term…
Abstract
Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.
Claims25
A semiconductor package comprising:
- a package substrate having a plurality of first and second connection terminals;
- a first semiconductor chip comprising an input/output circuit for sending and receiving signals to and from an outside of the semiconductor package;
- a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip comprising a memory cell region for storing data;
- a plurality of first through vias formed through the first semiconductor chip, the first through vias connecting the input/output circuit to the plurality of first connection terminals;
- a plurality of second through vias formed through the second semiconductor chip, the second through vias connecting the memory cell region to the input/output circuit;
- a plurality of third through vias formed through the first semiconductor chip, connected to the second connection terminals;
- and
- a plurality of fourth through vias formed through the second semiconductor chip, the fourth through vias being connected to the third through vias for providing a power signal and a ground signal to at least the second semiconductor chip,
- wherein the plurality of third through vias are dedicated to at least the second semiconductor chip and not electrically connected to the remainder of the first semiconductor chip to provide the power signal and the ground signal to the first semiconductor chip.
A multichip package comprising:
- a package substrate;
- a first chip on a surface of the package substrate, the first chip including a circuit;
- a stack of memory chips on the first chip;
- a power supply voltage conductor arranged in a stacking direction and passing through the first chip and the stack of memory chips and electrically connected to receive a power supply voltage;
- a reference voltage conductor arranged in a stacking direction and passing through the first chip and the stack of memory chips and electrically connected to receive a reference voltage;
- wherein the power supply voltage conductor is dedicated to the memory chips, the power supply voltage conductor connected to provide a power supply voltage to the memory chips,
- wherein the reference voltage conductor is dedicated to the memory chips, the reference voltage conductor connected to provide a reference voltage to the memory chips, and
- wherein the power supply voltage conductor and the reference voltage conductor each comprise a stack of through vias comprising a through via passing through the first chip and through vias passing through respective ones of the plurality of memory chips.
The multichip package of 13, wherein each memory chip of the stack of memory chips has at least one other chip of the stack of memory chips as an immediately neighboring chip.
A multichip package comprising:
- a package substrate;
- a first chip on a surface of the package substrate, the first chip including a circuit;
- a stack of memory chips, the stack of memory chips stacked on the first chip;
- a power supply voltage conductor arranged in a stacking direction and passing through the first chip and the stack of memory chips and electrically connected to receive a power supply voltage;
- a reference voltage conductor arranged in a stacking direction and passing through the first chip and the stack of memory chips and electrically connected to receive a reference voltage;
- wherein the power supply voltage conductor is electrically connected to provide the power supply voltage to at least one of the memory chips and is not electrically connected within the first chip to supply the power supply voltage to the first chip,
- wherein the reference voltage conductor is electrically connected to provide a reference voltage to at least one of the memory chips and is not electrically connected within the first chip to supply a reference voltage to the first chip, and
- wherein the power supply voltage conductor and the reference voltage conductor each comprise a stack of through vias including a first through via passing through the first chip and memory chip through vias passing through respective ones of the plurality of memory chips.
Dependencies are inferred from the claim text.