Row redundancy for content addressable memory having programmable interconnect structure
AssigneeNetLogic Microsystems, Inc.
InventorsVaradarajan Srinivasan, Sandeep Khanna
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Abstract
A content addressable memory (CAM) device includes an array having a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line, a spare CAM row including a plurality of CAM cells coupled to a spare match line, and row replacement circuitry configured to functionally replace a defective CAM row and each subsequent CAM row in the array with corresponding next adjacent CAM rows, wherein a last CAM row in the array is functionally replaced by the spare CAM row.
Claims19
A content addressable memory (CAM) device, comprising:
- an array having a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line;
- a spare CAM row including a plurality of CAM cells coupled to a spare match line;
- and
- row replacement circuitry configured to functionally replace a defective CAM row and each subsequent CAM row in the array with corresponding next adjacent CAM rows, wherein a last CAM row in the array is functionally replaced by the spare CAM row, wherein the row replacement circuitry comprises:
- a programmable interconnect routing structure (PRS) coupled to the CAM rows and the spare CAM row, the PRS configured to selectively route a match signal from any CAM row as an input match signal to any number of arbitrarily selected CAM rows or spare CAM row at the same time.
A content addressable memory (CAM) device, comprising:
- an array having at least one CAM block including a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line;
- a spare CAM row including a number of CAM cells coupled to a spare match lines;
- and
- a programmable interconnect routing structure (PRS) coupled to the CAM rows and configured to selectively route a match signal output from any CAM row to any number of other arbitrarily selected CAM rows at the same time, and further configured to functionally replace a defective CAM row with another CAM row in the array.
A content addressable memory (CAM) device, comprising:
- a plurality of CAM blocks, each CAM block including a number N of CAM rows, and each CAM row including a plurality of CAM cells coupled to a match line;
- a spare CAM row including a number of CAM cells coupled to a spare match lines;
- and
- a programmable interconnect routing structure (PRS) coupled to the CAM rows and configured to functionally replace a defective CAM row with another CAM row in the array, wherein the PRS is configured to functionally replace the defective CAM row in a first CAM block with a selected CAM row in a next adjacent CAM block.
Dependencies are inferred from the claim text.