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US 7,924,588 B2Granted
Content addressable memory with concurrent two-dimensional search capability in both row and column directions
AssigneeInternational Business Machines Corporation
InventorsIgor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort
Life of this patent
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Abstract
A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
Claims21
A content addressable memory (CAM) device, comprising:
- an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction;
- and
- the array of memo cells having first and second portions, the second portion configured to compare data presented along each row with data stored in each column, and indicate match results on each column of the array;
- wherein the first portion is configured to compare data presented along each column with data stored in each row, and to indicate match results on each row of the array, thereby resulting in a two-dimensional search capability of the array;
- and
- wherein the two-dimensional search capability of the array is concurrent in both row and column directions.
3 more elements
A ternary content addressable memory (TCAM) cell, comprising:
- a first SRAM storage device configured to store a first data bit and a second SRAM storage device configured to store a second data bit;
- a first NFET stack associated with the first SRAM storage device, and a second NFET stack associated with the second SRAM storage device, the first and second NFET stacks comprising compare circuitry configured to indicate match results of row-oriented search data presented to the cell;
- and
- a third NFET stack associated with the first SRAM storage device, and a fourth NFET stack associated with the second SRAM storage device;
- wherein the third and fourth NFET stacks are configured to perform one of:
- indicate match results of column-oriented search data presented to the cell in a two-dimensional search mode of operation;
- and
- concurrently read data stored in the SRAM storage devices during the presentation of row-oriented search data to the cell.
5 more elements
Dependencies are inferred from the claim text.