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US 7,924,260 B2Granted
Shift register, gate driving circuit with bi-directional transmission function, and LCD with double frame rate
AssigneeAu Optronics Corporation
InventorsMing-Hung Tu, Chih-Hsiang Yang
Life of this patent
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Abstract
A shift register applied on a double-frame-rate LCD is provided. The LCD includes an upper display area with c gate lines, a lower display area with d gate lines, and a gate driving circuit. The gate driving circuit includes a first shift register coupled to the corresponding x gate lines of the upper display area, a second shift register coupled to the corresponding y lines of the lower display area, and a third shift register coupled to the corresponding (c-x) gate lines of the upper display area and the corresponding (d-y) gate lines of the lower display area.
Claims10
A shift register comprising:
- a first transmission end for receiving a down-scanning enabling signal;
- a second transmission end for receiving the down-scanning enabling signal or an up-scanning enabling signal;
- a third transmission end for receiving the up-scanning enabling signal;
- a first switch comprising:
- a first end coupled to the first transmission end;
- a control end for receiving a direction signal indicating the up-scanning or the down-scanning enabling signal is received;
- and
- a second end for coupling to the first end of the first switch according to the direction signal;
- a first shift register module having m shift register units comprising:
- a first shift register unit comprising:
- a first input end coupled to the second end of the first switch;
- a second input end for receiving a clock signal;
- and
- an output end for outputting a first driving signal according to the signals on the first input end and the second input end of the first shift register unit;
- a pth shift register unit comprising:
- a first input end coupled to an output end of a (p−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a pth driving signal according to the signals on the first input end and the second input end of the pth shift register unit;
- and
- an mth shift register unit comprising:
- a first input end coupled to an output end of an (m−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting an mth driving signal according to the signals on the first input end and the second input end of the mth shift register unit;
- a second switch comprising:
- a first end coupled to the output end of the mth shift register unit;
- a control end for receiving a selection signal;
- and
- a second end for coupling to the first end of the second switch according to the selection signal;
- a second shift register module having n shift register units comprising:
- a second shift register unit comprising:
- a first input end coupled to the second end of the first switch;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a second driving signal according to the signals on the first input end and the second input end of the second shift register unit;
- a qth shift register unit comprising:
- a first input end coupled to an output end of a (q−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a qth driving signal according to the signals on the first input end and the second input end of the qth shift register unit;
- and
- an nth shift register unit comprising:
- a first input end coupled to an output end of an (n−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a nth driving signal according to the signals on the first input end and the second input end of the nth shift register unit;
- a third switch comprising:
- a first end coupled to the output end of the nth shift register;
- a control end for receiving the direction signal;
- and
- a second end coupled to the third transmission end of the shift register for coupling to the first end of the third switch according to the direction signal;
- a fourth switch comprising:
- a first end coupled to the output end of the nth shift register unit;
- a control end for an inversion of the direction signal;
- and
- a second end coupled to the first transmission end of the shift register for coupling to the first end of the fourth switch according to the inversion of the direction signal;
- a fifth switch comprising:
- a first end coupled to the second transmission end of the shift register;
- a control end for receiving the inversion of the direction signal;
- and
- a second end coupled to the first input end of the second shift register unit for coupling to the first end of the fifth switch according to the inversion of the direction signal;
- and
- a sixth switch comprising:
- a first end coupled to the output end of the nth shift register unit;
- a control end for receiving the inversion of the direction signal;
- and
- a second end coupled to the first input end of the first shift register unit for coupling to the first end of the sixth switch according to the inversion of the direction signal;
- wherein m, n, p, q are integers greater than 1 and 1<p<m, and 1<q<n.
66 more elements
A gate driving circuit with bi-directional transmission function comprising:
- a shift register comprising:
- a first transmission end for receiving a down-scanning enabling signal;
- a second transmission end for receiving the down-scanning enabling signal or an up-scanning enabling signal;
- a third transmission end for receiving the up-scanning enabling signal;
- a first switch comprising:
- a first end coupled to the first transmission end;
- a control end for receiving a direction signal indicating the up-scanning or the down-scanning enabling signal is received;
- and
- a second end for coupling to the first end of the first switch according to the direction signal;
- a first shift register module having m shift register units comprising:
- a first shift register unit comprising:
- a first input end coupled to the second end of the first switch;
- a second input end for receiving a clock signal;
- and
- an output end for outputting a first driving signal according to the signals on the first input end and the second input end of the first shift register unit;
- a pth shift register unit comprising:
- a first input end coupled to an output end of a (p−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a pth driving signal according to the signals on the first input end and the second input end of the pth shift register unit;
- and
- an mth shift register unit comprising:
- a first input end coupled to an output end of an (m−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting an mth driving signal according to the signals on the first input end and the second input end of the mth shift register unit;
- a second switch comprising:
- a first end coupled to the output end of the mth shift register unit;
- a control end for receiving a selection signal;
- and
- a second end for coupling to the first end of the second switch according to the selection signal;
- a second shift register module having n shift register units comprising:
- a second shift register unit comprising:
- a first input end coupled to the second end of the first switch;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a second driving signal according to the signals on the first input end and the second input end of the second shift register unit;
- a qth shift register unit comprising:
- a first input end coupled to an output end of a (q−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a qth driving signal according to the signals on the first input end and the second input end of the qth shift register unit;
- and
- an nth shift register unit comprising:
- a first input end coupled to an output end of an (n−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting an nth driving signal according to the signals on the first input end and the second input end of the nth shift register unit;
- a third switch comprising:
- a first end coupled to the output end of the nth shift register;
- a control end for receiving the direction signal;
- and
- a second end coupled to the third transmission end of the shift register for coupling to the first end of the third switch according to the direction signal;
- a fourth switch comprising:
- a first end coupled to the output end of the nth shift register unit;
- a control end for receiving inversion of the direction signal;
- and
- a second end coupled to the first transmission end of the shift register for coupling to the first end of the fourth switch according to the inversion of the direction signal;
- a fifth switch comprising:
- a first end coupled to the second transmission end of the shift register;
- a control end for receiving the inversion of the direction signal;
- and
- a second end coupled to the first input end of the second shift register unit for coupling to the first end of the fifth switch according to the inversion of the direction signal;
- a sixth switch comprising:
- a first end coupled to the output end of the nth shift register unit;
- a control end for receiving the inversion of the direction signal;
- and
- a second end coupled to the first input end of the first shift register unit for coupling to the first end of the sixth switch according to the inversion of the direction signal;
- and
- a data selection circuit coupled to the shift register for selectively and sequentially generating a plurality of gate driving signals according to driving signals generated by the shift register and the up-scanning enabling signal or the down-scanning enabling signal;
- wherein m, n, p, q are integers greater than 1 and 1<p<m, and 1<q<n.
68 more elements
An LCD with double frame rate comprising:
- an upper display area comprising c gate lines;
- a lower display area comprising d gate lines;
- a gate driving circuit comprising:
- a first shift register coupled to corresponding x lines of the upper display area for providing corresponding gate driving signals;
- a second shift register coupled to corresponding y lines of the lower display area for providing corresponding gate driving signals;
- and
- a third shift register coupled to corresponding (c-x) lines of the upper display area and corresponding (d-y) lines of the lower display area for providing corresponding gate driving signals;
- wherein c, d, x, y are integers greater than 1, and 1<x<c, and 1<y<d;
- wherein each shift register of the first, the second, and the third shift registers comprises:
- a first transmission end for receiving a down-scanning enabling signal;
- a second transmission end for receiving the down-scanning enabling signal or an up-scanning enabling signal;
- a third transmission end for receiving the up-scanning enabling signal;
- a first switch comprising:
- a first end coupled to the first transmission end;
- a control end for receiving a direction signal indicating the UP scanning or the down-scanning enabling signal is received;
- and
- a second end for coupling to the first end of the first switch according to the direction signal;
- a first shift register module having m shift register units comprising:
- a first shift register unit comprising:
- a first input end coupled to the second end of the first switch;
- a second input end for receiving a clock signal;
- and
- an output end for outputting a first driving signal according to the signals on the first input end and the second input end of the first shift register unit;
- a pth shift register unit comprising:
- a first input end coupled to an output end of a (p−1) shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a pth driving signal according to the signals on the first input end and the second input end of the pth shift register unit;
- and
- an mth shift register unit comprising:
- a first input end coupled to an output end of an (m−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting an mth driving signal according to the signals on the first input end and the second input end of the mth shift register unit;
- a second switch comprising:
- a first end coupled to the output end of the mth shift register unit;
- a control end for receiving a selection signal;
- and a second end for coupling to the first end of the second switch according to the selection signal;
- a second shift register module having n shift register units comprising:
- a second shift register unit comprising:
- a first input end coupled to the second end of the first switch;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a second driving signal according to the signals on the first input end and the second input end of the second shift register unit;
- a qth shift register unit comprising:
- a first input end coupled to an output end of a (q−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting a qth driving signal according to the signals on the first input end and the second input end of the qth shift register unit;
- and
- an nth shift register unit comprising:
- a first input end coupled to an output end of an (n−1)th shift register unit;
- a second input end for receiving the clock signal;
- and
- an output end for outputting an nth driving signal according to the signals on the first input end and the second input end of the nth shift register unit;
- a third switch comprising:
- a first end coupled to the output end of the nth shift register;
- a control end for receiving the direction signal;
- and a second end coupled to the third transmission end of the shift register for coupling to the first end of the third switch according to the direction signal;
- a fourth switch comprising:
- first end coupled to the output end of the nth shift register unit;
- a control end for receiving inversion of the direction signal;
- and
- a second end coupled to the first transmission end of the shift register for coupling to the first end of the fourth switch according to the inversion of the direction signal;
- a fifth switch comprising:
- a first end coupled to the second transmission end of the shift register;
- a control end for receiving the inversion of the direction signal;
- and
- a second end coupled to the first input end of the second shift register unit for coupling to the first end of the fifth switch according to the inversion of the direction signal;
- and
- a sixth switch comprising:
- a first end coupled to the output end of the nth shift register unit;
- a control end for receiving the inversion of the direction signal;
- and
- a second end coupled to the first input end of the first shift register unit for coupling to the first end of the sixth switch according to the inversion of the direction signal;
- wherein m, n, p, q are integers greater than 1 and 1<p<m, and 1<q<n.
73 more elements
Dependencies are inferred from the claim text.