Gate driving apparatus for preventing distortion of gate start pulse and image display device using the same and driving method thereof

An image display unit, comprising:

• a display panel having a plurality of pixel cells formed in portions defined by a plurality of gate and data lines formed perpendicularly;
• a gate driver which supplies a scan pulse to the gate line;
• a data driver which supplies a video signal to the data line;
• and
• a timing controller which controls the gate and data drivers,
• wherein the gate driver comprises:
• a start pulse generator which generates a second gate start pulse by a logic operation of a first gate start pulse and a gate output enable signal provided from the timing controller, wherein the second gate start pulse synchronizes with a first pulse of the gate output enable signal, the first pulse overlapping the first gate start pulse;
• a shift register including a plurality of flip-flops which generates a shift signal by sequentially shifting the second gate start pulse in accordance with a gate shift clock provided from the timing controller, wherein the second gate start pulse output from the start pulse generator is supplied to a first flip-flop among the plurality of flip-flops;
• and
• an output unit which outputs the shift signal to the gate line in accordance with the gate output enable signal,
• wherein the second gate start pulse is high state only when both the first gate start pulse and the gate output enable signal are in the high state, a pulse width of the gate output enable signal is the same as a pulse width of the second gate start pulse, and each pulse width of the gate output enable signal and the second gate start pulse is smaller than a pulse width of the first gate start pulse.

A driving method of a gate driving apparatus, comprising:

• a step 1:
• generating a second gate start pulse by performing a logic operation to a first gate start pulse and a gate output enable signal, wherein the second gate start pulse synchronizes with a first pulse of the gate output enable signal, the first pulse overlapping the first gate start pulse;
• a step 2:
• generating a shift signal by sequentially shifting the second gate start pulse in accordance with a gate shift clock by a shift register including a plurality of flip-flops, wherein the second gate start pulse output from a start pulse generator is supplied to a first flip-flop among the plurality of flip-flops;
• and
• a step 3:
• outputting the shift signal in accordance with the gate output enable signal,
• wherein the second gate start pulse is high state only when both the first gate start pulse and the gate output enable signal are in the high state, a pulse width of the gate output enable signal is the same as a pulse width of the second gate start pulse, and each pulse width of the gate output enable signal and the second gate start pulse is smaller than a pulse width of the first gate start pulse.

A driving method of an image display device including a display panel provided with a plurality of pixel cells formed in portions defined by a plurality of gate and data lines formed perpendicularly comprising:

• supplying a scan pulse to the gate line;
• and
• supplying a video signal to the data line in synchronization with the scan pulse,
• wherein the step of supplying the scan pulse to the gate line comprises:
• a step 1:
• generating a second gate start pulse by performing a logic operation to a first gate start pulse and a gate output enable signal, wherein the second gate start pulse synchronizes with a first pulse of the gate output enable signal, the first pulse overlapping the first gate start pulse;
• a step 2:
• generating a shift signal by sequentially shifting the second gate start pulse in accordance with a gate shift clock by a shift register including a plurality of flip-flops, wherein the second gate start pulse output from a start pulse generator is supplied to a first flip-flop among the plurality of flip-flops;
• and
• a step 3:
• outputting the shift signal to the gate line in accordance with the gate output enable signal,
• wherein the second gate start pulse is high state only when both the first gate start pulse and the gate output enable signal are in the high state, a pulse width of the gate output enable signal is the same as a pulse width of the second gate start pulse, and each pulse width of the gate output enable signal and the second gate start pulse is smaller than a pulse width of the first gate start pulse.