Single slope analog-to-digital converter
AssigneeKoninklijke Philips Electronics N.V.
InventorsMartijn F. Snoeij, Adrianus J. Mierop, Albert J. P. Theuwissen, Johannes H. Huijsing
Life of this patent
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Abstract
A single-slope ADC, particularly suitable for use in a massive-parallel ADC architecture in a readout circuit of a CMOS imager. A plurality of ramp signals are generated which define non-overlapping sub-ranges of the full input range. For each ADC channel, the sub-range in which the voltage of the input signal falls is determined, and the corresponding ramp signal is selected for use in the A/D conversion. Thus, the speed of the A/D conversion process can be increased and the power consumption decreased.
Claims12
An analog-to-digital converter (ADC) having an input range, the ADC comprising:
- means for receiving an analog input signal (Vin) having a value;
- ramp generating means for generating simultaneously a plurality of n ramp signals, wherein n is the number of ramp signals (Vramp1,2, . . . n) covering non-overlapping sub-ranges of a complete range of the input range;
- selection means for selecting one of said plurality of n ramp-signals (Vramp1,2, . . . n) whose sub-range includes the value of said analog input signal;
- a comparator for comparing said analog input signal (Vin) with said selected ramp signal (Vramp);
- and
- means, operating under the control of said comparator in response to the comparison of the analog input signal with the selected ramp signal of the plurality of n ramp signals, for outputting a digital representation of the value of said analog input signal.
A method of performing an analog-to-digital conversion with respect of an analog input signal having an input range, the method comprising:
- receiving an analog input signal having a value;
- generating simultaneously a plurality of n ramp signals, wherein n is the number of ramp signals (Vramp1,2, . . . n) covering non-overlapping sub-ranges of a complete range of the input range;
- selecting one of said plurality of n ramp-signals (Vramp1,2, . . . n) whose sub-range includes the value of said analog input signal;
- comparing said analog input signal with said selected ramp signal;
- and
- outputting, in response to the comparison of the analog input signal with the selected ramp signal of the plurality of n ramp signals, a digital representation of the value of said analog input signal.
A CMOS image sensor comprising a plurality of pixels, arranged in a matrix comprising rows and columns, and at least one readout circuit for reading out electrical signals generated by said pixels, said readout circuit comprising at least one analog-to-digital converter (ADC) having an input range, the ADC comprising means for receiving an electrical signal from a pixel, the electrical signal having an analog value, ramp generating means for generating simultaneously a plurality of n ramp signals, wherein n is the number of ramp signals (Vramp1,2 . . . n) covering non-overlapping sub-ranges of a complete range of input range, selection means for selecting one of said plurality of n ramp-signals (Vramp1,2, . . . n) whose sub-range includes the value of said electrical signal, a comparator for comparing said electrical signal with said selected ramp signal (Vramp), and means, operating under the control of said comparator in response to the comparison of the electrical signal with the selected ramp signal of the plurality of n ramp signals, for outputting a digital representation of the value of said electrical signal.
Dependencies are inferred from the claim text.