Integrated circuit device and electronic instrument

An integrated circuit comprising:

• an amplifier circuit that includes first to Nth (N is an integer equal to or larger than two) amplifiers and receives an input signal, the first to Nth amplifiers being cascaded;
• an A/D converter that performs an A/D conversion process on a signal amplified by the amplifier circuit;
• first to Nth D/A converters that are provided corresponding to the first to Nth amplifiers and used to perform an offset adjustment of the first to Nth amplifiers;
• and
• a control circuit that sets an offset adjustment of the first to Nth amplifiers using the first to Nth D/A converters and sets a gain adjustment of the first to Nth amplifiers,
• a 1LSB-equivalent voltage VLSB1 of an ith (i is an integer that satisfies 1≦i<N) D/A converter among the first to Nth D/A converters being higher than a 1LSB-equivalent voltage VLSB2 of an (i+1)th D/A converter among the first to Nth D/A converters that is provided in a subsequent stage of the ith D/A converter.

An integrated circuit device comprising:

• an amplifier circuit that includes first to Nth (N is an integer equal to or larger than two) amplifiers and receives an input signal, the first to Nth amplifiers being cascaded;
• an A/D converter that performs an A/D conversion process on a signal amplified by the amplifier circuit;
• first to Nth D/A converters that are provided corresponding to the first to Nth amplifiers and used to perform an offset adjustment of the first to Nth amplifiers;
• and
• a control circuit that sets an offset adjustment of the first to Nth amplifiers using the first to Nth D/A converters and sets a gain adjustment of the first to Nth amplifiers;
• first to Nth offset adjustment registers that are provided corresponding to the first to Nth amplifiers and store first to Nth offset adjustment data, the first to Nth offset adjustment data being used to perform an offset adjustment of the first to Nth amplifiers;
• and
• first to Nth gain adjustment registers that are provided corresponding to the first to Nth amplifiers and store first to Nth gain adjustment data, the first to Nth gain adjustment data being used to perform a gain adjustment of the first to Nth amplifiers.

An integrated circuit device comprising:

• an amplifier circuit that includes first to Nth (N is an integer equal to or larger than two) amplifiers and receives an input signal, the first to Nth amplifiers being cascaded;
• an A/D converter that performs an A/D conversion process on a signal amplified by the amplifier circuit;
• first to Nth D/A converters that are provided corresponding to the first to Nth amplifiers and used to perform an offset adjustment of the first to Nth amplifiers;
• a control circuit that sets an offset adjustment of the first to Nth amplifiers using the first to Nth D/A converters and sets a gain adjustment of the first to Nth amplifiers;
• a selector that selects an output signal among output signals from the first to Nth amplifiers, and outputs the selected output signal to the A/D converter as a selector output signal;
• and
• a determination circuit that determines whether or not a voltage of the output signal from each of the first to Nth amplifiers is within a determination voltage range specified by a high-potential-side determination voltage and a low-potential-side determination voltage,
• the control circuit instructing the selector to select an output signal among the output signals from the first to Nth amplifiers based on a determination result of the determination circuit.