Use of three phase clock in sigma delta modulator to mitigate the quantization noise folding
AssigneeTexas Instruments Incorporated
InventorAjay Kumar
Life of this patent
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Abstract
A differential sigma delta modulator operates by modulating an input signal by intermittently coupling a reference signal to the input signal using one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals. The modulated input signal is integrated using an integration capacitor to form an integrated value and the integrated value is compared to a threshold to form the one or more feedback signals. Parasitic capacitance of the one or more switches is initialized to an initial value prior to each intermittent coupling of the reference signal to the input signal using another non-overlapping clock signal.
Claims17
A method of operating a sigma delta modulator, comprising:
- modulating an input signal by intermittently coupling a reference signal to the input signal using one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals;
- integrating the modulated input signal using an integration capacitor to form an integrated value;
- amplifying the integrated value;
- comparing the integrated value to a threshold to form the one or more feedback signals;
- and
- initializing a parasitic capacitance of the one or more switches to an initial value prior to each intermittent coupling of the reference signal to the input signal using a third non-overlapping clock signal.
A system comprising a sigma delta modulator, the modulator comprising:
- feedback circuitry configured to modulate an input signal by intermittently coupling a reference signal to the input signal using one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals;
- filter circuitry configured to integrate the modulated input signal using an integration capacitor to form an integrated value;
- quantizer circuitry coupled to the filter configured to compare the integrated value to a threshold to form the one or more feedback signals;
- and
- initialization circuitry coupled to the feedback circuitry configured to initialize a parasitic capacitance of the one or more switches to an initial value prior to each intermittent coupling of the reference signal to the input signal using a third non-overlapping clock signal.
Dependencies are inferred from the claim text.