Semiconductor integrated circuit device, pattern detection method and serial-parallel conversion method

A semiconductor integrated circuit device comprising:

• a shift register configured to successively take in and hold input serial data on the basis of a first clock signal;
• at least one pattern detection section configured to detect at least one predetermined pattern contained in the serial data taken in the shift register;
• a timing determination section configured to, when the serial data held in the shift register is output by being converted into parallel data by using a second clock signal having a speed lower than that of the first clock signal, determine timing of conversion from the serial data to the parallel data on the basis of a result of detection performed by the at least one pattern detection section;
• and
• an output section configured to output parallel data formed from the serial data held in the shift register by using the second clock signal from the timing determination section, wherein the timing determination section is configured to start generating the second clock signal by the conversion timing.

A semiconductor integrated circuit device comprising:

• a shift register configured to successively take in and hold input serial data on the basis of a first clock signal;
• at least one pattern detection section configured to detect at least one predetermined pattern contained in the serial data taken in the shift register;
• and
• a timing determination section configured to, when the serial data held in the shift register is output by being converted into parallel data by using a second clock signal having a speed lower than that of the first clock signal, determine timing of conversion from the serial data to the parallel data on the basis of a result of detection performed by the at least one pattern detection section,
• wherein the timing determination section is configured to generate the second clock signal and to generate a load signal indicating the conversion timing, the semiconductor integrated circuit device further comprising an output section configured to take in the serial data held in the shift register by using the load signal from the timing determination section, and output the taken-in serial data by using the second clock signal from the timing determination section.

A pattern detection method comprising:

• taking serial data in a shift register and successively transferring the serial data;
• dividing a predetermined pattern in the serial data into one or more first-group bits and second-group bits and performing, when one or more bits of the serial data corresponding to the one or more first-group bits are taken in the shift register, a logical operation on values of the bits taken in to determine whether or not the serial data input to the shift register coincides with the one or more first-group bits;
• and
• determining, when one or more bits of the serial data corresponding to the one or more first-group bits are taken in the shift register, whether or not the serial data input to the shift register coincides with the one or more first-group bits by performing a logical operation on values of the bits taken in the shift register, and detecting, if it is determined by the logical operation that the serial data input to the shift register coincides with the one or more first- group bits, the predetermined pattern in the serial data by making determination on a bit-by-bit basis, each time a bit of the serial data is taken in the shift register, as to whether or not the value of the bit taken in coincides with the corresponding one of the second-group bits of the predetermined pattern.

A serial-parallel conversion method comprising:

• taking serial data in a shift register and successively transferring the serial data by using a first clock signal;
• detecting a predetermined pattern contained in the serial data in the course of transfer of the serial data;
• and
• converting, when the predetermined pattern is detected, the serial data held in the shift register into parallel data by using a second clock signal having a speed lower than that of the first clock signal and outputting the parallel data,
• wherein the determination of the predetermined pattern is made by dividing the predetermined pattern in the serial data into one or more first-group bits and second-group bits, by determining, by a logical operation, whether or not the serial data input to the shift register coincides with the one or more first-group bits, and
• by determining whether or not the serial data input to the shift register coincides with the second-group bits, by using the first clock signal and checking the bits of the serial data one by one.

A serial-parallel conversion method comprising:

• taking serial data in a shift register and successively transferring the serial data by using a first clock signal;
• detecting a predetermined pattern contained in the serial data in the course of transfer of the serial data;
• and
• converting, when the predetermined pattern is detected, the serial data held in the shift register into parallel data by using a second clock signal having a speed lower than that of the first clock signal and outputting the parallel data,
• wherein output of the parallel data is performed by supplying outputs from flip-flops in a plurality of stages constituting the shift register to flip-flops in a plurality of stages constituting an output section by using a load signal generated at a time at which the predetermined pattern is detected, and
• by outputting parallel data formed from the serial data held in the flip-flops in the plurality of stages constituting the output section by using the second clock signal.