High-speed serial interface circuitry for programmable integrated circuit devices

An integrated circuit comprising:

• programmable circuitry;
• and
• a channel of high-speed serial data signal transmitter circuitry that is hard-wired to always receive from the programmable circuitry a predetermined number of data bits in parallel for transmitting by the channel serially;
• wherein a portion of the programmable circuitry is programmed to received from other circuitry of the integrated circuit groups of parallel data bits and to output bits thus received in said predetermined number for application to the channel, each of which groups can include a number of bits having any of a plurality of programmably selectable ratios to the predetermined number;
• wherein the channel transmits the data bits serially at a serial bit rate and produces a first reference clock signal having a first frequency that is the serial bit rate divided by the predetermined number;
• wherein said portion of the programmable circuitry is responsive to the first reference clock signal to clock the predetermined number of data bits out of said portion to the channel;
• and wherein the programmable circuitry further comprises:
• phase-locked loop circuitry that receives the first reference clock signal and that is programmable to produce a second clock signal having a second frequency that has any one of the programmably selectable ratios to the first frequency.

An integrated circuit comprising:

• programmable circuitry;
• and
• a channel of high-speed serial data signal receiver circuitry that is hard-wired to include a parallel data output bus for always outputting to the programmable circuitry a predetermined number of data bits in parallel, said bits having been received by the channel serially;
• wherein a portion of the programmable circuitry is programmed to receive successive blocks of the predetermined number of parallel bits from the bus and to output bits thus received in successive groups of parallel bits, each of which groups can include a number of bits having any of a plurality of programmably selectable ratios to the predetermined number;
• wherein the channel receives the data bits serially at a serial bit rate and produces a first reference clock signal having a first frequency that is the serial bit rate divided by the predetermined number;
• wherein said portion of the programmable circuitry is responsive to the first reference clock signal to clock successive blocks received from the bus into said portion;
• and wherein the programmable circuitry further comprises:
• phase-locked loop circuitry that receives the first reference clock signal and that is programmable to produce a second clock signal having a second frequency that has any one of the programmably selectable ratios to the first frequency.

An integrated circuit comprising:

• programmable circuitry;
• and
• a channel of high-speed serial transmitter circuitry that is hard-wired to include a parallel data input bus for always receiving from the programmable circuitry a predetermined number of data bits in parallel, said bits being transmitted by the channel serially;
• wherein a portion of the programmable circuitry is programmed to receive successive groups of parallel bits and to output bits thus received to the bus in successive blocks of the predetermined number of parallel bits, each of which groups can include a number of bits having any of a plurality of programmably selectable ratios to the predetermined number;
• wherein the channel transmits the data bits serially at a serial bit rate and produces a first reference clock signal having a first frequency that is the serial bit rate divided by the predetermined number;
• wherein said portion of the programmable circuitry is responsive to the first reference clock signal to clock successive blocks out of said portion onto the bus;
• and wherein the programmable circuitry further comprises:
• phase-locked loop circuitry that receives the first reference clock signal and that is programmable to produce a second clock signal having a second frequency that has any one of the programmably selectable ratios to the first frequency.