Inter-stage matching network to enhance common mode stability

An amplifier comprising:

• a. a first stage differential amplifier having
• i. at least one first transistor, and
• ii. at least one second transistor,
• wherein said at least one first transistor and said at least one second transistor are arranged to form said first stage differential amplifier with a first stage common node;
• b. a second stage differential amplifier having
• i. at least one third transistor, and
• ii. at least one fourth transistor;
• wherein said at least one third transistor and said at least one fourth transistor are arranged to form said second stage differential amplifier with a second stage common node;
• c. an on-chip connection path arranged to connect the first stage common node to the second stage common node;
• d. a first transformation network comprising a first shunt component and a second shunt component, said first shunt component closer to said second stage than said second shunt component, an end of said first shunt component connected to a first node of said on-chip connection path and an end of said second shunt component connected to a second node of said on-chip connection path;
• and
• e. a second transformation network comprising a third shunt component and a fourth shunt component, said third shunt component closer to said second stage than said fourth shunt component, an end of said third shunt component connected to the first node of said on-chip connection path, and an end of said fourth shunt component connected to the second node of said on-chip connection path,
• wherein
• a first output of said first differential stage, associated with said at least one first transistor, is operatively connected to a first input of said second differential stage, associated with said third transistor, by said first transformation network,
• a second output of said first differential stage, associated with said at least one second transistor, is operatively connected to a second input of said second differential stage, associated with said fourth transistor, by said second transformation network, and
• wherein said on-chip connection path comprises a first resistor inserted between the second stage common node and the first node of the on-chip connection.