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US 7,924,087 B2Granted
Reference buffer circuit
AssigneeMediatek Inc.
InventorsWei-Hsuan Tu, Tzung-Hung Kang
Life of this patent
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Abstract
A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.
Claims24
A reference buffer circuit, comprising:
- a buffering stage, coupled to a first supply voltage and providing a high tracking voltage and a low tracking voltage respectively based on a high input voltage and a low input voltage;
- a first driving stage, coupled to a second supply voltage and driven by the high tracking voltage and the low tracking voltage to output a first high output voltage and a first low output voltage;
- a second driving stage, coupled to a third supply voltage and driven by the high tracking voltage and the low tracking voltage to output a second high output voltage and a second low output voltage;
- and
- a compensation unit,
- wherein the buffering stage comprises:
- a first NMOS transistor with its drain coupled to the first supply voltage;
- a first operational amplifier, having a first input end for receiving the high input voltage, a second input end coupled to a source of the first NMOS transistor, and an output end coupled to a gate of the first NMOS transistor for outputting the high tracking voltage;
- a first PMOS transistor with its drain coupled to a signal ground;
- and
- a second operational amplifier, having a first input end for receiving the low input voltage, a second input end coupled to a source of the first PMOS transistor, and an output end coupled to a gate of the first PMOS transistor for outputting the low tracking voltage;
- wherein a body of the first PMOS transistor is tied to a first bias voltage lower than the first supply voltage, and
- wherein the first driving stage comprises a second PMOS transistor with a body tied to a second bias voltage lower than the second supply voltage, the second driving stage comprises a third PMOS transistor with a body tied to a third bias voltage lower than the third supply voltage, and the compensation unit calibrates mismatch between the first and second driving stages by modifying the third bias voltage.
10 more elements
A reference buffer circuit, comprising:
- a buffering stage, having a first NMOS transistor and a first PMOS transistor for providing a high tracking voltage and a low tracking voltage respectively based on a high input voltage and a low input voltage;
- a first driving stage, having a second NMOS transistor and a second PMOS transistor respectively driven by the high tracking voltage and the low tracking voltage to output a first high output voltage and a first low output voltage;
- a second driving stage, having a third NMOS transistor and a third PMOS transistor respectively driven by the high tracking voltage and the low tracking voltage to output a second high output voltage and a second low output voltage;
- and
- a compensation unit,
- wherein a body of the first PMOS transistor is tied to a first bias voltage lower than a first supply voltage for the buffering stage, a body of the second PMOS transistor is tied to a second bias voltage lower than a second supply voltage for the first driving stage, and a body of the third PMOS transistor is tied to a third bias voltage lower than a third supply voltage for the second driving stage, and
- wherein the compensation unit calibrates mismatch between the first and second driving stages by modifying the third bias voltage.
4 more elements
A reference buffer circuit, comprising:
- a first driving stage, having a first MOS transistor and a second MOS transistor driven by a high tracking voltage and a low tracking voltage to output a first high output voltage and a first low output voltage;
- and
- a second driving stage, having a third MOS transistor and a fourth MOS transistor driven by the high tracking voltage and the low tracking voltage to output a second high output voltage and a second low output voltage;
- wherein a body of the second MOS transistor is tied to a first bias voltage lower than a first supply voltage for the first driving stage, and a body of the fourth MOS transistor is tied to a second bias voltage lower than a second supply voltage for the second driving stage, and
- wherein the second bias voltage is different from the first bias voltage.
2 more elements
A reference buffer circuit, comprising:
- a buffering stage, having a first MOS transistor and a second MOS transistor for providing a high tracking voltage and a low tracking voltage based on a high input voltage and a low input voltage;
- a first driving stage, having a third MOS transistor and a fourth MOS transistor driven by the high tracking voltage and the low tracking voltage to output a first high output voltage and a first low output voltage;
- a first bias voltage generator, arranged to provide a first bias voltage;
- and
- a second bias voltage generator, arranged to provide a second bias voltage;
- wherein a body of the second MOS transistor is tied to the first bias voltage generator, a body of the fourth MOS transistor is tied to the second bias voltage generator, and the bodies of the second and fourth MOS transistors are respectively biased by the first and second bias voltages.
3 more elements
A reference buffer circuit, comprising:
- a first driving stage, having a first MOS transistor and a second MOS transistor driven by a high tracking voltage and a low tracking voltage to output a first high output voltage and a first low output voltage;
- a second driving stage, having a third MOS transistor and a fourth MOS transistor driven by the high tracking voltage and the low tracking voltage to output a second high output voltage and a second low output voltage;
- a first bias voltage generator, arranged to provide a first bias voltage;
- and
- a second bias voltage generator, arranged to provide a second bias voltage;
- wherein a body of the second MOS transistor is tied to the first bias voltage generator, a body of the fourth MOS transistor is tied to the second bias voltage generator, and the bodies of the second and fourth MOS transistors are respectively biased by the first and second bias voltages.
3 more elements
Dependencies are inferred from the claim text.