Boosting circuit
AssigneePanasonic Corporation
InventorSeiji Yamahira
Life of this patent
Estimating the term…
Abstract
A boosting circuit configuration with high boosting efficiency is provided which is based on a boosting circuit that performs an operation in accordance with a two-phase clock and which includes a plurality (M≧4) of boosting cell sequences (units). A boosting cell in a K-th sequence (1≦K≦M) is controlled, depending on the potential of the output terminal of a boosting cell in a KA-th sequence (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). Thereby, before a clock input to the boosting cell in the K-th sequence goes from “L” to “H”, so that boosting is performed, a charge transfer transistor can be caused to go from the conductive state to the non-conductive state, so that a backflow of charges via charge transfer transistor can be prevented.
Claims34
A boosting circuit having backflow preventing cells arranged in M parallel sequences (M≧4), the backflow preventing cells performing a boosting operation in synchronization with a plurality of clock signals having different phases, wherein
- the backflow preventing cell provided in a K-th sequence (1≦K≦M), includes:
- an input terminal for receiving a voltage from a stage preceding the backflow preventing cell;
- an output terminal for supplying a voltage to an output terminal of the booting circuit;
- an intermediate terminal for supplying a voltage to another backflow preventing cell;
- a charge transfer unit provided between the input terminal or the output terminal, and the intermediate terminal;
- a boosting capacitance having two ends, one end being connected to the intermediate terminal of the backflow preventing cell, and the other end receiving a clock signal corresponding to the backflow preventing cell;
- a charge transfer transistor connected between the input terminal and the output terminal of the backflow preventing cell, and for transferring charges from the input terminal to the output terminal when the charge transfer transistor is in a conductive state;
- and
- a state control unit for controlling the charge transfer transistor, depending on an intermediate terminal voltage of a backflow preventing cell in a KA-th sequence (KA=(K−A) when (K−A)>0, and KA=(M−|K−A|) when (K−A)≦0) located A sequences before the K-th sequence (1≦A≦M/2−1:
- A is a natural number).
A boosting circuit having backflow preventing cells arranged in M parallel sequences (M≧4), the backflow preventing cells performing a boosting operation in synchronization with a plurality of clock signals having different phases, wherein
- the backflow preventing cell provided in a K-th sequence (1≦K≦M), includes:
- an input terminal for receiving a voltage from a stage preceding the backflow preventing cell;
- an output terminal for supplying a voltage to an output terminal of the booting circuit;
- an intermediate terminal for supplying a voltage to another backflow preventing cell;
- a charge transfer unit provided between the input terminal or the output terminal, and the intermediate terminal;
- a boosting capacitance having two ends, one end being connected to the intermediate terminal of the backflow preventing cell, and the other end receiving a clock signal corresponding to the backflow preventing cell;
- a charge transfer transistor connected between the input terminal and the output terminal of the backflow preventing cell, and for transferring charges from the input terminal to the output terminal when the charge transfer transistor is in a conductive state, and
- a state control unit having a first terminal and a second terminal, the intermediate terminal of a backflow preventing cell in a KA-th sequence (KA=(K−A) when (K−A)>0, and KA=(M−|K−A|) when (K−A)≦0) located A sequences before the K-th sequence (1≦A≦M/2−1:
- A is a natural number) being connected to the first terminal, and a gate of the charge transfer transistor being connected to the second terminal.
A boosting circuit having a plurality of clock signals having different phases, and a plurality of boosting cells arranged in M parallel sequences (M≧4) and L stages (L≧2), the boosting cells performing a boosting operation in synchronization with the plurality of clock signals, wherein
- one of the boosting cells includes:
- a boosting capacitance having two ends, one end being connected to an output terminal of the one of the boosting cells, and the other end receiving a clock signal corresponding to the one of the boosting cells;
- and
- a charge transfer transistor connected between the input terminal and the output terminal of the one of the boosting cells, wherein
- an output terminal of another one of the boosting cells in the same stage as the one of the boosting cells and in a first sequence of the sequences different from the one of the boosting cells is connected to a control terminal of a state control unit for controlling both an on state and an off state of the charge transfer transistor of the one of the boosting cells, and
- M boosting cells in the same stage as the one of the boosting cells are connected to one another so as to have a ring shape.
A boosting circuit having a plurality of clock signals having different phases, and a plurality of boosting cells arranged in M parallel sequences (M≧4) and L stages (L≧2), the boosting cells performing a boosting operation in synchronization with the plurality of clock signals, wherein
- one of the boosting cells includes:
- a boosting capacitance having two ends, one end being connected to an output terminal of the one of the boosting cells, and the other end receiving a clock signal corresponding to the one of the boosting cells;
- a charge transfer transistor connected between the input terminal and the output terminal of the one of the boosting cells;
- and
- a state control unit including for controlling both an on state and an off state of a charge transfer transistor of the boosting cell by, according to an output terminal of another one of the boosting cells in the same stage as the one of the boosting cells and in a first sequence of the sequences different from the one of the boosting cells, switching between the input terminal voltage of the one of the boosting cells, and an output terminal voltage of another one of the boosting cells in the same stage as the one of the boosting cells and in a second sequence of one of the sequences different from the one of the boosting cells.
A boosting circuit having a plurality of clock signals having different phases, and a plurality of boosting cells arranged in M parallel sequences (M≧4) and L stages (L≧2), the boosting cells performing a boosting operation in synchronization with the plurality of clock signals, wherein
- one of the boosting cells includes:
- a boosting capacitance having two ends, one end being connected to an output terminal of the one of the boosting cells, and the other end receiving a clock signal corresponding to the one of the boosting cells;
- and
- a charge transfer transistor connected between the input terminal and the output terminal of the one of the boosting cells, wherein
- according to a signal from an output terminal of another one of the boosting cells in the same stage as the one of the boosting cells and in a first sequence of the sequences different from the one of the boosting cells, a charge transfer transistor of the one of the boosting cells is set to be a non-conductive state, and then, a boosting operation of the one of the boosting cells is performed, said signal from the output terminal of said another one of the boosting cells controlling both the non-conductive state and a conductive state of the charge transfer transistor.
A boosting circuit having a plurality of clock signals having different phases, and backflow preventing cells arranged in M parallel sequences (M≧4) and L stages (L≧2), the boosting cells performing a boosting operation in synchronization with the plurality of clock signals, wherein
- one of the backflow preventing cells includes:
- an input terminal;
- an output terminal;
- an intermediate terminal;
- a charge transfer unit provided between the input terminal or the output terminal, and the intermediate terminal;
- a boosting capacitance having two ends, one end being connected to the intermediate terminal of the one of the backflow preventing cells, and the other end receiving a clock signal corresponding to the one of the backflow preventing cells;
- and
- a charge transfer transistor connected between the input terminal and the output terminal of the one of the backflow preventing cells,
- an intermediate terminal of another one of the backflow preventing cells in the same stage as the one of the backflow preventing cells and in a first sequence of the sequences different from the one of the backflow preventing cells is connected to a control terminal of a state control unit for controlling the charge transfer transistor of the one of the backflow preventing cells, and
- M backflow preventing cells in the same stage as the one of the backflow preventing cells are connected to one another so as to have a ring shape.
A boosting circuit having a plurality of clock signals having different phases, and backflow preventing cells arranged in M parallel sequences (M≧4) and L stages (L≧2), the boosting cells performing a boosting operation in synchronization with the plurality of clock signals, wherein
- one of the backflow preventing cells includes:
- an input terminal;
- an output terminal;
- an intermediate terminal;
- a charge transfer unit provided between the input terminal or the output terminal, and the intermediate terminal;
- a boosting capacitance having two ends, one end being connected to the intermediate terminal of the backflow preventing cell, and the other end receiving a clock signal corresponding to the backflow preventing cell;
- a charge transfer transistor connected between the input terminal and the output terminal of the backflow preventing cell;
- and
- a state control unit including for controlling a charge transfer transistor of the boosting cell by, according to an intermediate terminal of the another one of the backflow preventing cells in the same stage as the one of the backflow preventing cells and in a first sequence of the sequences different from the one of the backflow preventing cells, switching between an input terminal voltage of the one of the backflow preventing cells, and an intermediate terminal voltage of another one of the backflow preventing cells in the same stage as the one of the backflow preventing cells and in a second sequence of the sequences different from the one of the backflow preventing cells.
A boosting circuit having a plurality of clock signals having different phases, and backflow preventing cells arranged in M parallel sequences (M≧4) and L stages (L≧2), the boosting cells performing a boosting operation in synchronization with the plurality of clock signals, wherein
- one of the backflow preventing cell includes:
- an input terminal;
- an output terminal;
- an intermediate terminal;
- a charge transfer unit provided between the input terminal or the output terminal, and the intermediate terminal;
- a boosting capacitance having two ends, one end being connected to the intermediate terminal of the backflow preventing cell, and the other end receiving a clock signal corresponding to the backflow preventing cell;
- and
- a charge transfer transistor connected between the input terminal and the output terminal of the backflow preventing cell, wherein
- according to an intermediate terminal of another one of backflow preventing cells in the same stage as the one of the backflow preventing cells and in a first sequence of the sequences different from the one of the backflow preventing cells, a charge transfer transistor of the one of the backflow preventing cells is set to be a non-conductive state, and then, a boosting operation of the one of the backflow preventing cells is performed.
Dependencies are inferred from the claim text.