Negative analog switch design
AssigneeSTMicroelectronics Asia Pacific Pte Ltd
InventorDianbo Guo
Life of this patent
Estimating the term…
Abstract
A transmission gate includes first and second MOS transistors of opposite conductivity type coupled in parallel with each other. Each transistor includes a body connection that is separately biased by corresponding first and second biasing circuits. The first biasing circuit generates a first bias voltage having a voltage level that is generated as a function of the signal at the first node and a first (for example, positive) reference voltage. The second biasing circuit generates a second bias voltage having a voltage level that is generated as a function of the signal at the first node and a second (for examples ground) reference voltage.
Claims15
A circuit, comprising:
- a first node adapted to receive a signal;
- a second node adapted to output the signal;
- and
- a transmission gate formed solely of first and second MOS transistors coupled in parallel with each other between the first node and second node, the first MOS transistor being of a first conductivity type and having a first body connection, the second MOS transistor being of a second conductivity type and having a second body connection;
- a first bias circuit adapted to generate a first bias voltage for application to the first body connection, that first bias voltage being generated as a function of the signal at the first node;
- and
- a second bias circuit adapted to generate a second bias voltage for application to the second body connection, that second bias voltage being generated as a function of the signal at the first node;
- wherein the first bias circuit comprises:
- third and fourth cross-coupled MOS transistors of the first conductivity type, wherein a gate of the third transistor is coupled to a positive reference voltage node and a gate of the fourth transistor is coupled to receive the signal from the first node, and wherein drains of the third and fourth cross-coupled MOS transistors are connected together and directly connected to the first body connection.
A circuit comprising:
- a first node adapted to receive a signal;
- a second node adapted to output the signal;
- and
- a transmission gate formed solely of first and second MOS transistors coupled in parallel with each other between the first node and second node, the first MOS transistor being of a first conductivity type and having a first body connection, the second MOS transistor being of a second conductivity type and having a second body connection;
- a first bias circuit adapted to generate a first bias voltage for application to the first body connection, that first bias voltage being generated as a function of the signal at the first node;
- and
- a second bias circuit adapted to generate a second bias voltage for application to the second body connection, that second bias voltage being generated as a function of the signal at the first node;
- wherein the second bias circuit comprises:
- fifth and sixth cross-coupled MOS transistors of the second conductivity type and wherein a gate of the fifth transistor is coupled to a ground reference voltage node and a gate of the sixth transistor is coupled to receive the signal from the first node.
A circuit comprising:
- a first node adapted to receive a signal;
- a second node adapted to output the signal;
- and
- a transmission gate formed solely of first and second MOS transistors coupled in parallel with each other between the first node and second node, the first MOS transistor being of a first conductivity type and having a first body connection, the second MOS transistor being of a second conductivity type and having a second body connection;
- a first bias circuit adapted to generate a first bias voltage for application to the first body connection, that first bias voltage being generated as a function of the signal at the first node;
- and
- a second bias circuit adapted to generate a second bias voltage for application to the second body connection, that second bias voltage being generated as a function of the signal at the first node;
- wherein the first bias circuit comprises:
- third and fourth cross-coupled MOS transistors of the first conductivity type and wherein a gate of the third transistor is coupled to a positive reference voltage node and a gate of the fourth transistor is coupled to receive the signal from the first node;
- and
- wherein the second bias circuit comprises:
- fifth and sixth cross-coupled MOS transistors of the second conductivity type and wherein a gate of the fifth transistor is coupled to a ground reference voltage node and a gate of the sixth transistor is coupled to receive the signal from the first node.
A circuit comprising:
- a first node;
- a second node;
- and
- a transmission gate formed solely of first and second MOS transistors coupled in parallel with each other between the first node and second node, the first MOS transistor being of a first conductivity type and having a first body connection, the second MOS transistor being of a second conductivity type and having a second body connection;
- a first bias circuit adapted to generate a first bias voltage for application to the first body connection, that first bias voltage being generated as a function of the signals at the first and second nodes;
- and
- a second bias circuit adapted to generate a second bias voltage for application to the second body connection, that second bias voltage being generated as a function of the signals at the first and second nodes;
- wherein the first bias circuit comprises:
- third and fourth cross-coupled MOS transistors of the first conductivity type,. wherein a gate of the third transistor is coupled to a third node and a gate of the fourth transistor is coupled to a fourth node, and wherein voltages at the third and fourth nodes are generated as a function of the signals at the first and second nodes and a positive reference voltage node.
A circuit comprising:
- a first node;
- a second node;
- and
- a transmission gate formed solely of first and second MOS transistors coupled in parallel with each other between the first node and second node, the first MOS transistor being of a first conductivity type and having a first body connection, the second MOS transistor being of a second conductivity type and having a second body connection;
- a first bias circuit adapted to generate a first bias voltage for application to the first body connection, that first bias voltage being generated as a function of the signals at the first and second nodes;
- and
- a second bias circuit adapted to generate a second bias voltage for application to the second body connection, that second bias voltage being generated as a function of the signals at the first and second nodes;
- wherein the second bias circuit comprises:
- fifth and sixth cross-coupled MOS transistors of the second conductivity type wherein a gate of the fifth transistor is coupled to a fifth node and a gate of the sixth transistor is coupled to a sixth node, and wherein voltages at the fifth and sixth nodes are generated as a function of the signals at the first and second nodes and a ground reference voltage node.
A circuit comprising:
- a first node;
- a second node;
- and
- a transmission gate formed solely of first and second MOS transistors coupled in parallel with each other between the first node and second node, the first MOS transistor being of a first conductivity type and having a first body connection, the second MOS transistor being of a second conductivity type and having a second body connection;
- a first bias circuit adapted to generate a first bias voltage for application to the first body connection, that first bias voltage being generated as a function of the signals at the first and second nodes;
- and
- a second bias circuit adapted to generate a second bias voltage for application to the second body connection, that second bias voltage being generated as a function of the signals at the first and second nodes;
- wherein the first bias circuit comprises:
- third and fourth cross-coupled MOS transistors of the first conductivity type, wherein a gate of the third transistor is coupled to a third node and a gate of the fourth transistor is coupled to a fourth node, and wherein voltages at the third and fourth nodes are generated as a function of the signals at the first and second nodes and a positive reference voltage node;
- and
- wherein the second bias circuit comprises:
- fifth and sixth cross-coupled MOS transistors of the second conductivity type, wherein a gate of the fifth transistor is coupled to a fifth node and a gate of the sixth transistor is coupled to a sixth node, and wherein voltages at the fifth and sixth nodes are generated as a function of the signals at the first and second nodes and a ground reference voltage node.
A circuit, comprising:
- a first node adapted to receive a signal;
- a second node adapted to output the signal;
- and
- a transmission gate formed solely of first and second MOS transistors coupled in parallel with each other between the first node and second node, the first MOS transistor being of a first conductivity type and having a first body connection, the second MOS transistor being of a second conductivity type and having a second body connection;
- a first bias circuit adapted to generate a first bias voltage for application to the first body connection, that first bias voltage having a first variable voltage level that is equal to a positive reference voltage if the signal received at the first node is below a first threshold and transitions, when the signal received at the first node exceeds the first threshold, to a voltage in excess of the positive reference voltage and proportional to the voltage of the signal received at the first node;
- and
- a second bias circuit adapted to generate a second bias voltage for application to the second body connection, that second bias voltage having a second variable voltage level that is equal to a ground reference voltage if the signal received at the first node exceeds a second threshold and transitions, when the signal received at the first node is below the second threshold, to a voltage less than the ground reference voltage and proportional to the voltage of the signal received at the first node.
Dependencies are inferred from the claim text.