Semiconductor device
AssigneeRenesas Electronics Corporation
InventorMasaki Kojima
Life of this patent
Estimating the term…
Abstract
A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R1 connects the gate to the source of the switching transistor. When a voltage not smaller than a predetermined value is generated across the resistance element R1 at turn-on, due to a parasitic capacitance existing between a power supply terminal. Vcc and the internal grounding wire GW, the switching transistor can be turned on to turn off the output transistor.
Claims14
A semiconductor device which comprises an output MOS transistor formed in a semiconductor substrate of a first conductivity type and a diffusion region of a second conductivity type formed in the semiconductor substrate forming a pn-junction therebetween, the semiconductor substrate being connected to a power supply terminal, the diffusion region being connected to a ground terminal, comprising:
- a switching MOS transistor including a source-drain path connected between a gate and a source of the output MOS transistor, and a gate, the source of the output MOS transistor being connected to an output terminal;
- an internal ground wire connected between the gate of the switching MOS transistor and the ground terminal;
- and
- an electric potential difference generating circuit connected to the internal ground wire and the gate of the switching MOS transistor at a first end thereof and connected to the source of the switching MOS transistor at a second end thereof,
- wherein the switching MOS transistor is configured to be turned ON when a potential of the internal ground wire is raised due to a parasitic capacitance existing between the power supply terminal and internal ground wire caused by the pn-junction.
A semiconductor device, comprising:
- an output MOS transistor including a source-drain path connected between a power supply terminal and an output terminal, the output MOS transistor being to provide an output current for an external load through the output terminal, the drain being formed in a semiconductor substrate of a first conductivity type;
- a switching MOS transistor including a source-drain path connected between a gate and the source of the output MOS transistor, and a gate, the source of the switching MOS transistor being coupled with the output terminal;
- an internal ground wire coupled between the gate of the switching MOS transistor and a ground terminal;
- an electric potential difference generating circuit coupled with the internal ground wire and the gate of the switching MOS transistor at a first end thereof and with the source of the switching MOS transistor at a second end thereof;
- and
- a diffusion region of a second conductivity type formed in the semiconductor substrate forming a pn-junction therebetween, the diffusion region being coupled with the ground terminal,
- wherein the switching MOS transistor is configured to be turned ON when a potential of the internal ground wire is raised due to a parasitic capacitance existing between the power supply terminal and internal ground wire caused by the pn-junction.
Dependencies are inferred from the claim text.