Driving configuration of a switch

An ultrasonic transducer, comprising:

• a first switch including first and second transistors coupled to each other and including first and second intrinsic diodes, respectively;
• a driving circuit configured to drive said first switch, wherein the driving circuit comprises first and second output terminals coupled to the first switch and configured to supply the first switch with a first control signal for driving said first switch in a first working state and a second control signal for driving said switch in a second working state;
• and
• a latch circuit coupled between respective common gate and conduction terminals of said first and second transistors and configured to supply said common gate terminal with said first and second control signals, respectively, according to said working state for turning off, and respectively turning on, said first and second transistors, wherein said latch circuit comprises:
• a set resistance and a reset resistance;
• a flip-flop coupled to said common conduction terminal and having:
• a reset terminal coupled to said first output terminal of said driving device and to said common conduction terminal by the reset resistance;
• a set terminal coupled to said second output terminal of said driving device and to said common conduction terminal by the set resistance;
• and
• an output terminal coupled to said common gate terminal;
• and
• an activation circuit connected to said set and reset terminals of the flip-flop and to said common conduction terminal and configured to dynamically short-circuit said set and reset resistances during falling edges of at least one of the first and second control signals applied to the first switch.

A switch circuit, comprising:

• a switch having first and second transistors coupled to one another, the first and second transistors sharing a common conduction terminal;
• and
• a driving circuit coupled to the switch, the driving circuit comprising:
• a first current source coupled to a first latch transistor and coupled to a control terminal of a second latch transistor;
• a second current source coupled to the second latch transistor and to a control terminal of the first latch transistor;
• the first and second latch transistors each being coupled to the common conduction terminal of the first and second transistors;
• and
• first and second clamp circuits coupled between the respective control terminals of the first and second latch transistors and the common conduction terminal.

A latch circuit, comprising

• a set resistance and a reset resistance;
• a first circuit node;
• a flip-flop including:
• a reset terminal coupled to the circuit node by the reset resistance;
• a set terminal coupled to said first circuit node by the set resistance, the reset and set terminals being configured to be driven by first and second control signals, respectively;
• and
• an output terminal;
• and
• an activation circuit coupled to said set and reset terminals of the flip-flop and to said first circuit node and configured to dynamically short-circuit said set and reset resistances during falling edges of at least one of the first and second control signals.