Level shifter circuit

A level shifter circuit in which gates of two NMOS transistors, sources of which are connected to a circuit ground, are input terminals to which two input signals having a complementary relation generated by an internal circuit, which operates with a first power supply, are respectively input, a gate of one of two PMOS transistors, sources of which are connected to a second power supply having voltage higher than that of the first power supply, and a drain of the other of the two PMOS transistors are connected to each other and a drain of one of the two PMOS transistors and a gate of the other of the two PMOS transistors are connected to each other, and one of drain connecting ends of the two NMOS transistors and the two PMOS transistors is an output terminal for outputting an output signal by the second power supply corresponding to a signal by the first power supply input to one of the two input terminals, the level shifter circuit comprising:

• a comparator that operates with the first power supply and determines coincidence and non-coincidence of a voltage level of the input signal to one of the two input terminals and a voltage level of the output signal from the output terminal;
• and
• a substrate bias circuit that operates with the first power supply or the second power supply and boosts voltages of substrate terminals of the two NMOS transistors to voltage higher than circuit ground potential in a period in which the comparator determines that the voltage levels do not coincide with each other.