Data recovery circuit

A data recovery circuit, comprising:

• an input data phase detection circuit for extracting, as a gate signal, a signal synchronized with input data from the input data and outputting the gate signal;
• a gated N-phase oscillator for generating N-phase clocks obtained by dividing a bit width of the input data into N-phase clocks in phase synchronization using the gate signal output from the input data phase detection circuit;
• N data discriminating and reproducing circuits for sampling the input data based on the N-phase clocks output from the gated N-phase oscillator and outputting sampled data;
• a continuous clock generation circuit for generating a continuous clock which is a reference clock;
• N continuous clock synchronization circuits for synchronizing the sampled data output from the N data discriminating and reproducing circuits with the continuous clock output from the continuous clock generation circuit and outputting the synchronized sampled data as phase synchronization data;
• and
• a phase selector for selecting, from the phase synchronization data output from the N continuous clock synchronization circuits, phase synchronization data having an optimum discrimination phase with a largest phase margin with respect to the input data and outputting the selected phase synchronization data as recovery data.