Delay control circuit and delay control method
AssigneeRenesas Electronics Corporation
InventorSeiichi Watarai
Life of this patent
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Abstract
A delay control circuit in which steady phase error can be eliminated has a first variable delay circuit and a first phase control circuit. The delay control circuit further includes a second variable delay circuit disposed in either a first or second clock path, and a second phase control circuit arranged so as to form an additional feedback loop, which is for canceling steady phase error produced by the first phase control circuit, with respect to the first clock path or second clock path using a delay value applied to the second variable delay circuit.
Claims20
A delay control circuit comprising:
- a first clock path in which a first variable delay circuit is disposed,
- a second clock path in which the first variable delay circuit does not intervene, and
- a first phase control circuit for matching a phase of a first clock that is output from the first clock path with a phase of a second clock that is output from the second clock path, by using a delay value applied to the first variable delay circuit;
- a second variable delay circuit disposed in either one of the first and second clock paths;
- and
- a second phase control circuit arranged to form a feedback loop to cancel steady phase error produced by the first phase control circuit, with respect to the first clock path or second clock path, by controlling a second delay value applied to said second variable delay circuit.
A method of eliminating steady phase error in a delay control circuit including a first phase control circuit for matching the phase of a first clock that is output from a first clock path in which a first variable delay circuit is disposed and a phase of a second clock that is output from a second clock path in which the first variable delay circuit does not intervene, said method comprising:
- matching phases of the first and second clocks by the first phase control circuit using a delay value applied to the first variable delay circuit;
- and
- matching a phase of a third clock, output from the first clock path or second clock path from any position inclusive of starting and end points thereof, and a phase of a fourth clock, output from a second variable delay circuit disposed in either one of the first and second clock paths, by adjusting a second delay value applied to the second variable delay circuit, by a second phase control circuit provided separate from the first phase control circuit, wherein the second phase control circuit cancels steady phase error produced by the first phase control circuit.
A delay control circuit comprising:
- a first phase control circuit matching a phase of a first clock signal with a phase of a second clock signal by applying a first control signal to a first variable delay circuit, the first clock signal being output from a first clock path and the second clock signal being output from a second clock path, the first variable delay circuit being disposed on the first clock path, and the first variable delay circuit not intervening in the second clock path;
- a second variable delay circuit disposed in the first clock path or the second clock path;
- and
- a second phase control circuit arranged to form a feedback loop to cancel steady phase error produced by the first phase control circuit, with respect to the first clock path or second clock path, by applying a second control signal to said second variable delay circuit.
Dependencies are inferred from the claim text.