Exact frequency translation using dual cascaded sigma-delta modulator controlled phase lock loops

A frequency translator to perform frequency conversion on an input clock signal, comprising:

• a first variable frequency divider having inputs for the input clock signal and for a control signal, the first variable frequency divider performing a frequency conversion upon the input clock signal by a ratio determined by the control signal,
• a first sigma delta modulator having an input for parameters representing integer and fractional portions of a frequency conversion ratio to be performed by the first variable frequency divider, the sigma delta modulator generating the control signal to the first variable frequency divider;
• a first PLL having an input coupled to an output of the first variable frequency divider, an output and a feedback path
• a second PLL having an input coupled to an output of the first PLL, an output and a feedback path extending from the second PLL's output to a second input of the second PLL,
• a second variable frequency divider provided in the feedback path of the second PLL, having an input coupled to the PLL output and an output coupled to the second PLL input, having another input for a second control signal, the second variable frequency divider performing a frequency conversion upon the a clock signal at its first input by a ratio determined by the second control signal, and
• a second sigma delta modulator having an input for parameters representing integer and fractional portions of a frequency conversion ratio to be performed by the second variable frequency divider, the sigma delta modulator generating the control signal to the second variable frequency divider.

A multi-channel frequency translator, comprising:

• a plurality of input branches, each comprising:
• a first variable frequency divider having an input for a respective clock signal and an input for a control signal, the first variable frequency divider performing a frequency conversion upon the respective clock signal by a ratio determined by the control signal, and
• a first sigma delta modulator having an input for parameters representing integer and fractional portions of a frequency conversion ratio to be performed by the first variable frequency divider, the sigma delta modulator generating the control signal to the first variable frequency divider;
• a selector to propagate an output signal a variable frequency divider of a selected branch;
• a PLL having a first input coupled to an output of the first variable frequency divider, an output and a feedback path extending from the PLL output to a second PLL input,
• a second variable frequency divider provided in the feedback path of the PLL, having an input coupled to the PLL output and an output coupled to the second PLL input, having another input for a second control signal, the second variable frequency divider performing a frequency conversion upon the a clock signal at its first input by a ratio determined by the second control signal, and
• a second sigma delta modulator having an input for parameters representing integer and fractional portions of a frequency conversion ratio to be performed by the second variable frequency divider, the sigma delta modulator generating the control signal to the second variable frequency divider.