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US 7,924,067 B2Granted
Low current wide VREF range input buffer
AssigneeRound Rock Research, LLC
InventorsTimothy B. Cowles, Steve Casper
Life of this patent
Estimating the term…
Abstract
A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.
Claims10
A differential input buffer, comprising:
- a buffer circuit having separate p- and n-channel differential amplifiers arranged to each receive a pair of input signals, the p- and n-channel differential amplifiers each being at least partially self-biased;
- first and second pairs of enabling series transistors, wherein the p- and n-channel differential amplifiers are each coupled to a respective one of the first and second pairs of enabling series transistors, each of the first and second pairs of enabling series transistors having a gate for receiving an enabling signal, and wherein each pair of enabling series transistors comprises a pair of n-channel transistors coupled to ground;
- at least one of the p-channel differential amplifier and n-channel differential amplifier being coupled to an enable transistor;
- and
- a first output terminal for combining outputs of the p- and n-channel differential amplifiers to form a first output of the differential input buffer, the first output terminal being coupled to at least one pair of output series transistors.
2 more elements
A memory circuit comprising:
- an input buffer circuit, said input buffer circuit comprising:
- a buffer circuit having separate p- and n-channel differential amplifiers, the separate p- and n-channel differential amplifiers are each at least partially self-biased;
- and
- first and second pairs of enabling series transistors, wherein the p- and n-differential amplifiers are each coupled to a respective one of the pairs of enabling series transistors, each of the pairs of enabling series transistors having a gate for receiving an enabling signal, and wherein each pair of enabling series transistors comprises a pair of n-channel transistors coupled to ground,
- wherein outputs of the differential amplifiers are combined to form a first output of the input buffer circuit and the first output is coupled to at least one pair of output series transistors.
2 more elements
A method of operating an input buffer, comprising:
- at least partially self-biasing a pair of separate p- and n-channel differential amplifiers;
- enabling at least one of the p- and n-channel differential amplifiers, the p- and n-differential amplifiers being coupled to a respective pair of enabling series transistors, each pair of enabling series transistors having a gate for receiving an enabling signal, and wherein each pair of enabling series transistors comprises a pair of n-channel transistors coupled to ground;
- detecting an input signal;
- comparing the input signal with a reference signal using the separate p and n-channel differential amplifiers;
- and
- providing the results of the comparison as a first output signal.
3 more elements
Dependencies are inferred from the claim text.