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US 7,924,066 B2Granted
Low speed, load independent, slew rate controlled output buffer with no DC power consumption
AssigneeFairchild Semiconductor Corporation
InventorsNickole A. Gagne, James B. Boomer, Roy L. Yarbrough
Life of this patent
Estimating the term…
Abstract
An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.
Claims3
An output buffer, comprising:
- an inverter connected to provide an output in response to receiving a buffer input;
- a pull up output transistor having a drain connected to provide a buffer output;
- a first resistor connected between the inverter output and the gate of the pull up transistor;
- a first feedback capacitor connected between the gate of the pull up transistor and the buffer output;
- a pull down output transistor having a drain connected to the buffer output;
- a second resistor connected between the inverter output and the gate of the pull up transistor;
- a second feedback capacitor connected between the gate of the pull down transistor and the buffer output;
- a third transistor having a source connectable to a power supply, a gate connected to the input signal, and a drain connected to the gate of the pull up transistor, and
- a fourth transistor having a source connectable to a ground, a gate connected to the input signal, and a drain connected to the gate of the pull down transistor,
- wherein current is driven through the first capacitor to slow the rise of the output voltage in response to the buffer input going high and current is driven through the second capacitor to slow the fall of the output voltage in response to the buffer input going low.
7 more elements
Dependencies are inferred from the claim text.