US 7,924,057 B2Granted

Logic system for DPA resistance and/or side channel attack resistance

AssigneeThe Regents of the University of California

InventorsIngrid Verbauwhede, Kris J. V. Tiri

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Abstract

DPA-resistant logic circuits and routing are described. An architecture and methodology are suitable for integration in a common automated EDA design tool flow. The architecture and design methodology can be used in logic circuits, gate arrays, FPGAs, cryptographic processors, etc. In one embodiment, the implementation details of how to create a secure encryption module can be hidden from the designer. The designer is thus, able to write the code for the design of DPA-resistant logic circuits using the same design techniques used for conventional logic circuits. Contrary to other complicated DPA -blocking techniques, the designer does not need specialized knowledge and understanding of the methodology. In one embodiment, the automated design flow generates a secure design from a Verilog or VHDL netlist. The resulting encryption module has a relatively constant power consumption that does not depend on the input signals and is thus relatively independent of which logic operations are performed.

Claims22

Dependent claims

A Wave Dynamic Differential Logic, comprising:

a plurality of differential logic cells arranged in a combinatorial logic tree and each having inverted combinatorial data-bearing inputs and corresponding non-inverted combinatorial data-bearing inputs, each of said plurality of differential logic cells configured to provide one or more inverted logic outputs and corresponding one or more non-inverted logic outputs, each of said plurality of differential logic cells configured to receive a precharge wave and/or a predischarge wave on said inverted combinatorial data-bearing inputs and non-inverted combinatorial data-bearing inputs of the respective differential logic cell and to propagate said precharge wave and/or said predischarge wave from said inverted combinatorial data-bearing inputs and corresponding non-inverting combinatorial data-bearing inputs of the respective differential logic cell to said inverted logic outputs and said non-inverted logic outputs of the respective differential logic cell,
wherein each of said plurality of differential logic cells is configured to receive and propagate said precharge wave and/or said predischarge wave during a precharge and/or pre-discharge phase, and is further configured to, during an evaluation phase, receive differential data on its inverted combinatorial data bearing inputs and its corresponding non-inverted combinatorial data-bearing inputs and evaluate said differential data to produce differential output data on its inverted logic outputs and its non-inverted logic outputs,
wherein said precharge wave and/or said predischarge wave is encoded in data received on the inverted and non-inverted combinatorial data-bearing inputs of each of said plurality of differential logic cells, and
wherein each of said plurality of differential logic cells is precharged or predischarged without distributing a separate precharge or predischarge signal to the plurality of differential logic cells.

1 more element

A Wave Dynamic Differential Logic, comprising:

a plurality of differential logic cells arranged in a combinatorial logic tree and each having inverted combinatorial data-bearing inputs and corresponding non-inverted combinatorial data-bearing inputs, each of said plurality of differential logic cells configured to provide one or more inverted logic outputs and corresponding one or more non-inverted logic outputs;
and
a precharge operator comprising first and second outputs and configured to receive a precharge signal and differential data comprising inverted differential data and corresponding non-inverted differential data, the precharge operator configured, during an evaluation phase, to provide the inverted differential data on the first output and the non-inverted differential data on the second output, and, during a precharge phase, to provide the precharge signal on the first and second outputs;
a differential logic register comprising a first output and a second output and configured to:
during the precharge phase, to receive a precharge signal and, in response to said precharge signal, to generate a pre-charge wave and provide the pre-charge wave to the combinatorial logic tree on the first second outputs to pre-charge and propagate through each of said plurality of differential logic cells from said inverted inputs and non-inverted inputs of the respective differential logic cell to said inverted logic outputs and non-inverted logic outputs of the respective differential logic cell;
and
during the evaluation phase, to provide the differential data to the combinatorial logic tree on the first and second outputs;
and
wherein said precharge wave is encoded in data received on the inverted and non-inverted combinatorial data-bearing inputs of each of the plurality of differential logic cells and each of said plurality of differential logic cells is precharged without distributing a separate precharge signal to any of the plurality of differential logic cells.

6 more elements

A Wave Dynamic Differential Logic, comprising:

a plurality of differential logic cells arranged in a combinatorial logic tree and each having combinatorial data-bearing inverted inputs and corresponding non-inverted combinatorial data-bearing inputs, each of said plurality of differential logic cells configured to provide one or more inverted logic outputs and corresponding one or more non-inverted logic outputs;
and
a predischarge operator comprising first and second outputs, and configured to receive a predischarge signal and differential data comprising inverted differential data and corresponding non-inverted differential data, the predischarge operator configured, during an evaluation phase, to provide the inverted differential data on the first output and the non-inverted differential data on the second output, and, during a predischarge phase, to provide the predischarge signal on the first and second outputs;
a differential logic register comprising first a second outputs and configured to:
during the predischarge phase, to receive a pre-discharge signal and, in response to said pre-discharge signal, to generate a pre-discharge wave and provide the predischarge wave to the combinatorial logic tree on the first and second outputs to pre-discharge and propagate through each of said differential logic cells from said inverted inputs and non-inverted inputs of the respective differential logic cell to said inverted logic outputs and non-inverted logic outputs of the respective differential logic cell;
and
during the evaluation phase, to provide the differential data to the combinatorial logic tree on the first and second outputs;
and
wherein said predischarge wave is encoded in data received on the inverted and non-inverted combinatorial data-bearing inputs of each of the plurality of differential logic cells and each of said plurality of differential logic cells is predischarged without distributing a separate predischarge signal to the plurality of differential logic cells.

6 more elements

A Divided Wave Dynamic Differential Logic DPA-resistant logic circuit, comprising:

a first single-ended logic tree comprising a plurality of first combinatorial data-bearing logic tree inputs and a plurality of first logic tree outputs and configured to, during an evaluation phase, receive inverted input data and corresponding non-inverted input data on said first combinatorial data-bearing logic tree inputs and to produce first output data on said first logic tree outputs, the first logic tree comprising a first plurality of logic gates;
and
a single-ended dual of said first single-ended logic tree connected in parallel with the first single-ended logic tree and comprising a plurality of dual combinatorial data-bearing logic tree inputs and a plurality of dual logic tree outputs and configured to, during said evaluation phase, receive said inverted input data and said corresponding non-inverted input data on said dual combinatorial data-bearing logic tree inputs and produce inverted first output data on said dual logic tree outputs, the dual of said first logic tree comprising a second plurality of logic gates, the first output data comprising single-ended non-inverted output data and the inverted first output data comprising single-ended corresponding inverted output data,
said first logic tree and said dual of said first logic tree further configured to, during a precharge and/or pre-discharge phase, receive a precharge wave and/or a pre-discharge wave on said first combinatorial data-bearing logic tree inputs and said dual combinatorial data-bearing logic tree inputs and propagate said precharge wave and/or pre-discharge wave through each of the first plurality of logic gates and each of the second plurality of logic gates to said first logic tree outputs and said dual logic tree outputs,
wherein said precharge wave is encoded in data received on the combinatorial data-bearing logic tree inputs of the first logic tree and the dual combinatorial data-bearing logic tree inputs of the second logic tree, and
wherein each of said first plurality of logic gates and each of said second plurality of logic gates is precharged or pre-discharged without distributing a separate precharge or pre-discharge signal to the first plurality of logic gates or to the second plurality of differential logic gates.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/586,846Filed 11 Feb 2005 · us provisional application
Priority: 13 Feb 2004
Published: US 2008/0224727 A118 Sep 2008
Granted: 12 Apr 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 30/394
Circuit design at the physical level: routing
G06F 7/00
Methods or arrangements for processing data by operating upon the order or
H04L 9/003
Countermeasures against attacks on cryptographic mechanisms: for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
G06F 2207/7266
Countermeasures against side channel or fault attacks: hardware adaptation, e.g. dual rail logic; calculate add and double simultaneously