Latency measurements for wireless communications
AssigneeLattice Semiconductor Corporation
InventorsJames Doubler, Michael Hammer, Jin Zhang
Life of this patent
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AssigneeLattice Semiconductor Corporation
InventorsJames Doubler, Michael Hammer, Jin Zhang
Estimating the term…
A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.
A programmable logic device (PLD), comprising:
A field programmable gate array (FPGA), comprising:
A programmable logic device, comprising:
Dependencies are inferred from the claim text.