Memory controller that controls termination in a memory device

A memory controller comprising:

• a data interface to output write data onto a data line coupled to a data input of a memory device;
• a command/address interface to output, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device;
• and
• a termination control output to assert a first termination control signal on a termination control signal line coupled to the memory device to cause the memory device to either (i) couple a first termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is to be received within the memory device or (ii) couple a second termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is not to be received within the memory device.

A memory controller comprising:

• a data interface to output write data onto a first data line;
• a first termination control output to assert or deassert a first termination control signal on a first termination control line;
• and
• a command/address interface to output commands to a first memory device coupled to the first data line and the first termination control line, the commands including one or more programming commands that indicate (i) a first termination impedance to be coupled to the first data line by the first memory device if the first termination control signal is asserted and the write data is directed to the first memory device;
• and (ii) a second termination impedance to be coupled to the first data line by the first memory device if the first termination control signal is asserted and the write data is directed to a memory device other than the first memory device.

A memory controller comprising:

• means for outputting write data onto a data line coupled to a data input of a memory device;
• means for outputting, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device;
• and
• means for asserting a first termination control signal on a termination control signal line coupled to the memory device to cause the memory device to either (i) couple a first termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is to be received within the memory device or (ii) couple a second termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is not to be received within the memory device.