Configurable emphasis for high-speed transmitter driver circuitry

Circuitry for giving pre-emphasis to a serial data signal comprising:

• first circuitry responsive to each successive bit in the serial data signal for causing a first electrical current flow indicative of said each successive bit;
• delay circuitry for delaying said each successive bit by one unit interval (“UI”) to produce a succession of delayed bits;
• second circuitry responsive to each successive delayed bit for causing a second electrical current flow indicative of said each successive delayed bit;
• and
• circuitry for making a selection between (1) combining and (2) not combining the first and second current flows such that when the current flows are combined, successive bits in a serial data output signal are based on the combined current flows, and when the current flows are not combined, successive bits in the serial data output signal are based on only one of the first and second current flows.

Circuitry for transmitting a serial data signal comprising:

• circuitry for giving de-emphasis to a bit that has a same data value as an immediately preceding bit;
• circuitry for selectively giving pre-emphasis to a bit that has a different data value than an immediately preceding bit;
• and
• circuitry for enabling the circuitry for selectively giving pre-emphasis only when the serial data signal has a bit rate that is less than a threshold bit rate.

Circuitry for transmitting a serial data signal comprising:

• circuitry for transmitting selected bits in the serial data signal with de-emphasis;
• circuitry for selectively transmitting selected bits in the serial data signal with pre-emphasis;
• and
• circuitry for enabling the circuitry for selectively transmitting only when the serial data signal has a bit rate that is less than a threshold bit rate.