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US 7,924,022 B2Granted
Evaluation board and failure location detection method
AssigneeFujitsu Limited
InventorHiroyuki Fujimoto
Life of this patent
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Abstract
An evaluation board, on which is mounted a chip to be evaluated is provided. Particularly, the evaluation board includes a monitoring window for monitoring a power supply part, a ground part, and a surface of the chip, a first signal input part for inputting signals to the chip, and a second signal input part for inputting signals to the chip, wherein the second signal input part is placed as to sandwich said monitoring window between itself and the first signal input part.
Claims7
An evaluation board, on which is mounted a chip to be evaluated, said evaluation board comprising:
- a first signal input part having a plurality of signal input lands for inputting a first signal to said chip;
- a second signal input part having a plurality of signal input lands for inputting a second signal to said chip;
- a monitoring window placed between the first signal input part and the second signal input part for monitoring the surface of the chip mounted on the evaluation board;
- a power supply part having a plurality of power supply lands for supplying power to the chip mounted on the evaluation board, the power supply part is placed between the second signal input part and the monitoring window;
- and
- a ground part having a plurality of ground lands for grounding the chip mounted on the evaluation board, the ground part is placed between the second signal input part and the monitoring window, wherein
- all of the power supply lands and the ground lands are placed between the second signal input part and the monitoring window, and no signal input lands are placed between the monitoring window and any of the power supply lands or the ground lands.
4 more elements
Dependencies are inferred from the claim text.