DC-DC converters with transient response control

#1. Field of the Invention

#The invention relates to a direct-current (DC) to direct-current (DC) converter, and more particularly to a DC-DC converter capable of transient response control according to the variation of output voltage of the DC-DC converter.

#2. Description of the Related Art

#The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

#FIG. 1 is an embodiment of a DC-DC converter with a single-phase PWM channel according to the invention;

#FIGS. 2A and 2B are two embodiments of transient boost circuits;

#FIG. 1 shows an embodiment of a DC-DC converter with a single-phase PWM channel according to the invention. The converter 100 may comprise a ramp oscillator 102, a PWM comparator 104, a logic circuit 106, drivers 108 and 110, NMOS transistors 112 and 114, a buck circuit 116, a feedback circuit 118, a compensation circuit 120, an error amplifier 122, and a transient boost circuit 124. The feedback circuit 118 may comprise resistors that divide an output voltage VOUT to generate a feedback voltage FB. The error amplifier 122 compares voltage FB with a reference voltage VREF to generate a signal COMP. The compensation circuit 120 can mitigate the variations of the signal COMP. The signal COMP may increase while voltage VOUT decreases, and decrease while voltage VOUT increases. The PWM comparator 104 can be regarded as a PWM generator to generate a PWM signal according to the output voltage VOUT. The ramp oscillator 102 may generate a saw-tooth or a triangle signal as a ramp signal. The PWM comparator 104 compares the ramp signal generated from the ramp oscillator 102 with the signal COMP to generate the signal PWM. The signal PWM is at a high level when the ramp signal is lower than the signal COMP; otherwise, the signal PWM is at a low level when the ramp signal is higher than the signal COMP. The transient boost circuit 124 receives the voltage VOUT and then generates a signal V1 according to the variation of the voltage VOUT. The logic circuit 106 can be a logic gate such as an OR gate, and receives the signal V1 and the signal PWM to generate a switching signal. The switching signal is at a high level, if either the signal V1 or the signal PWM is at a high level, and the switching signal is at a low level, if both the signal V1 and the signal PWM are at a low level. The drivers 108 and 110 and the NMOS transistors 112 and 114 together form a switching device to convert the input voltage VDD to a driving signal according to the switching signal. The driving signal is a voltage at a node between the NMOS transistors 112 and 114. The drivers 108 and 110 receive the output signal from the logic circuit 106 to alternatively turn on the NMOS transistors 112 and 114. Accordingly, the driving signal is equal to the input voltage VDD when the NMOS transistor 112 is turned on and the NOMS transistor 114 is turned off, and the driving signal is equal to the ground voltage when the NMOS transistor 114 is turned on and the NMOS transistor 112 is turned off. The buck circuit 116 comprises an inductor 126 coupled to the NMOS transistors 112 and 114, a capacitor 128 coupled to the inductor 126, and a resistor 130 coupled between the capacitor 128 and the ground. The buck circuit 116 receives the driving signal to convert the input voltage VDD to the output voltage VOUT. The output voltage VOUT can be supplied to a load needed to be driven by direct current.

#The transient boost circuit 124 comprises an offset adjustment circuit 132 and a comparator 134. The offset adjustment circuit 132 receives the voltage VOUT and then generates a transient boost voltage TB having an offset voltage corresponding to the voltage VOUT. The comparator 134 can be an operational amplifier. The comparator 134 receives the voltage VOUT at its inverting terminal and the voltage TB at its non-inverting terminal, and compares the voltage VOUT with the voltage TB to generate an adjusting signal V1. FIG. 2A shows an embodiment of transient boost circuit 124. The offset adjustment circuit 132 may comprise a current source 202, a resistor 204, and a capacitor 206. The input offset voltage VOFFSET between the voltage VOUT and the voltage TB is determined by the resistance of the resistor 204 and the current generated by the current source 202. The resistor 204 and the capacitor 206 together form a low-pass filter (LPF) to stabilize the voltage TB, so that the voltage TB can be fixed at a voltage having a voltage offset VOFFSET corresponding to a steady state of the voltage VOUT. Referring to FIG. 3, the voltage VOUT is initially kept at a steady state when the load connected to the DC-DC converter 100 is unchanged, and the transient boost voltage TB has a voltage offset VOFFSET corresponding to the voltage VOUT. When the voltage VOUT drops due to current load event, the voltage TB does not respond immediately because of the low-pass filter. Accordingly, the comparator 134 can generate a high level signal as an adjusting signal V1 if the voltage VOUT drops lower than the voltage TB. On the contrary, the comparator 134 can generate a low level signal as the signal V1 if the voltage VOUT becomes higher than the voltage TB. The positive pulse of the signal V1 forces the NMOS transistor 112 to be turned on to supply more current to the load, thereby pulling up the voltage VOUT. One advantage of the embodiment is that the transient boost circuit 124 has a quicker response to the current load event than the signal PWM, because the signal COMP varies with the voltage VOUT with a time delay.

#In another embodiment, the offset adjustment can be implemented in the comparator 134. Referring to FIG. 2B, an offset voltage source 208 inside the comparator 134 is used to provide the input offset voltage VOFFSET between the voltage VOUT and the voltage TB, and the capacitor 210 is used to stabilize the voltage TB. To implement the internal offset voltage source 208 in the comparator 134, the size of the transistors at the input stage of the comparator 134 can be made to be mismatched to generate an input offset. For example, the offset voltage can be set as 100˜200 mV, with the offset value dependent on the design rule according to realistic implementations.