Fault protection circuit, method of operating a fault protection circuit and a voltage regulator employing the same

#The present disclosure is directed, in general, to voltage regulation and, more specifically, to a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator employing the circuit or the method.

#A low dropout voltage (LDO) regulator is a linear DC voltage regulator characterized by having a small input to output differential voltage, which reduces power dissipation associated with lower overall power supply efficiency. The LDO regulator also uses only a few critical components that include an error amplifier connected to a reference voltage and a feedback signal that is proportional to an output voltage. The error amplifier maintains the output voltage in a normal operating range as load current varies by responding to an error signal that results from comparing the reference voltage against the feedback signal. The error amplifier in turn generates an appropriate control signal to control the flow of current in a power stage and maintain a regulated value of the output voltage. LDO regulators are broadly applied in harsh environments that may contain opportunity for the regulated output to become faulted. Regulators can deal with some fault conditions. Nevertheless, improvements in dealing with special fault conditions would prove beneficial in the art.

#Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with a voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.

#For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

#FIG. 1 illustrates a system diagram of a voltage regulator as provided by one embodiment of the disclosure;

#FIG. 2 illustrates a sectioned view of an isolation structure containing a gate pull-down MOS transistor as may be employed with the voltage regulator of FIG. 1; and

#Fault conditions within a regulation and normal operating range of a voltage regulator are typically accommodated by normal functioning of the voltage regulator. Embodiments of the present disclosure provide protection for the voltage regulator that may encounter fault conditions to voltages that are outside its regulation and normal operating range. Embodiments discussed below protect the voltage regulator from two types of fault conditions on its output node.

#A current overload fault condition results from shorting the output node to a voltage that is lower than the lowest voltage employed in the voltage regulator. The current overload fault condition, if not limited, may cause an output current of at least one regulator component to increase to the point of regulator failure. Similarly, a voltage breakdown fault condition results from shorting the output node to a voltage higher than a line input voltage to the voltage regulator. The voltage breakdown fault condition, if not limited, may cause at least one critical regulator component to fail due to voltage overload.

#FIG. 1 illustrates a system diagram of a voltage regulator 100 as provided by one embodiment of the disclosure. Although embodiments of the present disclosure may employ transistors of either polarity, an example employing n-type transistors is discussed with respect to FIG. 1. The voltage regulator 100 includes an error amplifier 105, a feedback signal generator 110 and a fault protection circuit 115. The error amplifier 105 includes a control signal output 106, a first differential input 107 connected to a reference voltage VREF and a second differential input 108 connected to a feedback signal VF. In the present embodiment, the error amplifier 105 is connected between a positive supply voltage VEA and ground, as shown. In this embodiment, the feedback signal generator 110 provides the feedback signal VF corresponding to a scaled-down version of a regulated output voltage VOUT on an output node 112 of the voltage regulator 100. This scaled-down version of the regulated output voltage VOUT is compared with the reference voltage VREF to generate a control signal on the control signal output 106.