Semiconductor system-in-a-package containing micro-layered lead frame

A semiconductor system-in-package, comprising:

• a land pad array comprising a middle portion and an outer portion;
• a first die containing an integrated circuit device resting on the middle portion of the land pad array;
• a second die containing an integrated circuit device disposed over the first die and resting on routing leads that are connected to the outer portion of the land pad array;
• a third die containing an integrated circuit device disposed on the backside of the second die, the third die electrically connected to the outer portion of the land array by wire bonds;
• a passive device or a discrete device resting on an outer portion of the land pad array;
• and
• a molding material comprising a first portion partially encapsulating the land pad array and the first die and a second portion encapsulating the routing leads, the second die, the third die, the wire bonds, and the passive or discrete device.

An electronic device, comprising:

• a semiconductor package comprising:
• a land pad array comprising a middle portion and an outer portion;
• a first die containing an integrated circuit device resting on the middle portion of the land pad array;
• a second die containing an integrated circuit device disposed over the first die and resting on routing leads that are connected to the outer portion of the land pad array;
• a third die containing an integrated circuit device disposed on the backside of the second die, the third die electrically connected to the outer portion of the land array by wire bonds;
• a passive device or a discrete device resting on an outer portion of the land pad array, and a molding material;
• and
• a printed circuit board connected to the land pad array.

A method for making semiconductor package, comprising:

• providing a lead frame containing an array of vias, device pads, and thermal pads;
• attaching a first die containing an integrated circuit device to a die attach pad of the leadframe;
• providing a first molding material around the array of vias, device pads, thermal pads, and the first die to leave the upper surfaces of the array of vias, device pads, thermal pads exposed;
• providing routing leads from the vias and the device pads to the backside of the first die;
• attaching a passive device or a discrete device to the device pads;
• and
• attaching a second die containing an integrated circuit device to the routing leads;
• attaching a third die containing an integrated circuit to the backside of the second die;
• connecting the third die to the vias and the device pads by wire bonds;
• providing a second molding material to encapsulate the routing leads, the second die, the third die, the wire bonds, and the passive or discrete device;
• and
• etching the lead frame to form a land pad array.