Method and structure for reducing contact resistance between silicide contact and overlying metallization
AssigneeInternational Business Machines Corporation
InventorsChristian Lavoie, Conal E. Murray, Kenneth P. Rodbell
Life of this patent
Estimating the term…
Abstract
A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy).
Claims6
A semiconductor structure comprising:
- a semiconductor substrate including at least one field effect transistor disposed thereon, said semiconductor substrate including silicide contact regions located adjacent said at least one field effect transistor;
- an insulating interlayer located on said semiconductor substrate and extending atop said at least one field effect transistor, said insulating interlayer having contact openings exposing said silicide contact regions;
- a metal germanide-containing contact material within said contact openings;
- and
- a diffusion barrier located on at least wall portions of said contact openings, said diffusion barrier separates said metal germanide-containing contact material from said silicide contact regions, wherein a region near bottom portions of each contact opening includes atomic species to minimize the Schottky barrier height at the contact opening/diffusion barrier interface.
A semiconductor structure comprising:
- a semiconductor substrate including at least one field effect transistor disposed thereon, said semiconductor substrate including silicide contact regions located adjacent said at least one field effect transistor;
- an insulating interlayer located on said semiconductor substrate and extending atop said at least one field effect transistor, said insulating interlayer having contact openings exposing said silicide contact regions;
- a metal germanide-containing contact material within said contact openings;
- and
- a diffusion barrier located on at least wall portions of said contact openings, said diffusion barrier separates said metal gennanide-containing contact material from said silicide contact regions, wherein a region near a top portion of each contact opening includes atomic species to minimize the Schottky barrier height at the contact opening/diffusion barrier interface.
Dependencies are inferred from the claim text.