Semiconductor devices having active elements with raised semiconductor patterns and related methods of fabricating the same

A semiconductor device comprising:

• a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate;
• an insulating isolation structure in the semiconductor substrate wherein the insulating isolation structure surrounds sidewalls of the semiconductor region;
• an interlayer insulating layer on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, wherein the interlayer insulating layer has first and second spaced apart element holes exposing respective first and second portions of the semiconductor region;
• a first semiconductor pattern in the first element hole on the first exposed portion of the semiconductor region;
• and
• a second semiconductor pattern in the second element hole on the second exposed portion of the semiconductor region;
• wherein a surface portion of the first semiconductor pattern opposite the semiconductor substrate and a surface portion of the second semiconductor pattern opposite the semiconductor substrate have a same conductivity type, wherein a first portion of the first semiconductor pattern is between a second portion of the first semiconductor pattern and the semiconductor region, wherein a first portion of the second semiconductor pattern is between a second portion of the second semiconductor pattern and the semiconductor region, and wherein the first portions of the first and second semiconductor patterns have an impurity concentration that is lower than an impurity concentration of the second portions of the first and second semiconductor patterns and that is lower than an impurity concentration of the semiconductor region.

A semiconductor device comprising:

• a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate;
• an insulating isolation structure in the semiconductor substrate wherein the insulating isolation structure surrounds sidewalls of the semiconductor region;
• an interlayer insulating layer on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, wherein the interlayer insulating layer has first and second spaced apart element holes exposing respective first and second portions of the semiconductor region;
• a first semiconductor pattern in the first element hole on the first exposed portion of the semiconductor region;
• and
• a second semiconductor pattern in the second element hole on the second exposed portion of the semiconductor region;
• wherein a surface portion of the first semiconductor pattern opposite the semiconductor substrate and a surface portion of the second semiconductor pattern opposite the semiconductor substrate have a same conductivity type, wherein the first and second semiconductor patterns and the semiconductor region define elements of a bipolar junction transistor, wherein a surface of the first semiconductor pattern opposite the semiconductor substrate defines an emitter of the bipolar junction transistor, wherein a surface of the second semiconductor pattern opposite the substrate defines a collector of the bipolar junction transistor, and wherein the semiconductor region defines a base of the bipolar junction transistor.

A semiconductor device comprising:

• a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate;
• an insulating isolation structure in the semiconductor substrate wherein the insulating isolation structure surrounds sidewalls of the semiconductor region;
• an interlayer insulating layer on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, wherein the interlayer insulating layer has first and second spaced apart element holes exposing respective first and second portions of the semiconductor region;
• a first semiconductor pattern in the first element hole on the first exposed portion of the semiconductor region;
• and
• a second semiconductor pattern in the second element hole on the second exposed portion of the semiconductor region;
• wherein a surface portion of the first semiconductor pattern opposite the semiconductor substrate and a surface portion of the second semiconductor pattern opposite the semiconductor substrate have a same conductivity type, wherein a surface of the first semiconductor pattern opposite the semiconductor substrate defines an emitter/collector of a first bipolar junction transistor, wherein a surface of the second semiconductor pattern opposite the semiconductor substrate defines an emitter/collector of a second bipolar junction transistor, and wherein the semiconductor region defines a shared base of the first and second bipolar junction transistors.

A semiconductor device comprising:

• a first semiconductor region in a semiconductor substrate;
• a second semiconductor region in the first semiconductor region wherein the first and second semiconductor regions have different conductivity types;
• an insulating isolation structure in the semiconductor substrate, wherein the insulating isolation structure surrounds sidewalls of the second semiconductor region, and wherein a depth of the first semiconductor region into the substrate is greater than a depth of the insulating isolation structure into the substrate;
• an interlayer insulating layer on the semiconductor substrate, on the first and second semiconductor regions, and on the insulating isolation structure wherein the interlayer insulating layer has an element hole therethrough exposing a portion of the second semiconductor region;
• and
• a semiconductor pattern in the element hole wherein a P-N junction is defined between the second semiconductor region and a portion of the semiconductor pattern in the element hole;
• wherein a surface of the semiconductor pattern opposite the substrate defines an emitter/collector of a bipolar junction transistor, and wherein the second semiconductor region defines a base of the bipolar junction transistor.