Semiconductor device including high voltage and low voltage MOS devices
AssigneeSamsung Electronics Co., Ltd.
InventorsChanSam Chang, Shigenobu Maeda, HeonJong Shin, ChangBong Oh
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Abstract
Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.
Claims15
A semiconductor device, comprising:
- high voltage asymmetric NMOS and PMOS devices and low voltage NMOS and PMOS devices disposed on a substrate and separated by a plurality of isolation structures disposed in the substrate to a first depth;
- wherein a drain region of the high voltage NMOS device and a channel region of the low voltage PMOS device are characterized by a first dopant implantation of second depth, and a drain region of the high voltage PMOS device and a channel region of the low voltage NMOS device are characterized by a second dopant implantation of third depth, and wherein the second and third depths are less than the first depth.
Dependencies are inferred from the claim text.