Semiconductor device with non-volatile memory function and method of manufacturing the same

A semiconductor device comprising:

• a semiconductor substrate having a first conductivity type drain area at a first exposed surface, a first conductivity type layer between the drain area and a second exposed surface of the semiconductor substrate opposite from the first exposed surface, a second conductivity type layer between the first conductivity type layer and the second exposed surface, and a first conductivity type source area at the second exposed surface of the semiconductor substrate;
• a plurality of trenches through the source area, the second conductivity type layer, and the first conductivity type layer;
• a floating gate in each of the plurality of trenches, the floating gates extending beyond the second exposed surface;
• an insulating layer on an outer surface of the floating gates;
• a tunneling gate intersecting and overlapping each of the floating gates;
• a control gate intersecting and overlapping each of the floating gates, spaced apart from and not overlapping with the tunneling gate;
• and
• sidewall tips on or over the semiconductor substrate, at intersections of the tunneling gate and each floating gate, configured to move or pass electrons to the floating gates under conditions for programming the floating gates, the sidewall tips comprising silicon and having a height less than a height by which the floating gates extend beyond the second exposed surface.

A method of manufacturing a semiconductor device, the method comprising the steps of:

• forming a plurality of trenches in a semiconductor substrate, the semiconductor substrate having a second conductivity type silicon layer, and the trenches extending through the second conductivity type silicon layer;
• forming a plurality of floating gates in the trenches in the semiconductor substrate and extending above the semiconductor substrate;
• forming an oxide layer on an entire surface of the semiconductor substrate, including an outer surface of the floating gates;
• forming a polysilicon layer on an entire surface of the semiconductor substrate;
• forming a first photoresist pattern on or over the semiconductor substrate;
• selectively etching the polysilicon layer, thereby forming (i) a tunneling gate and a control gate directly on the oxide layer, intersecting and overlapping each of the floating gates, the tunneling gate and control gate being spaced apart from each other and not overlapping with each other, and (ii) sidewall spacers along sidewalls of each of the floating gates, at opposite sides of the tunneling gate;
• selectively etching the sidewall spacers, thereby forming sidewall tips at opposite sides of the tunneling gate, the sidewall tips having a height less than a distance by which the floating gates extend beyond the semiconductor substrate;
• and
• implanting first conductivity type impurity ions into a first exposed surface of the semiconductor substrate, thereby forming a source area, and into a second exposed surface of the semiconductor substrate opposite from the first exposed surface, thereby forming a drain area.