Array substrate of liquid crystal display device and method of manufacturing the same

A method of manufacturing an array substrate of a fringe field switching (FFS) mode liquid crystal display device, wherein the array substrate comprises a base substrate and a common electrode, a gate line, a data line, a thin film transistor, a passivation layer and a pixel electrode of “” shape, which are all formed on the base substrate;

• the thin film transistor comprises a gate electrode, a source electrode and a drain electrode;
• the gate electrode is connected with the gate line;
• the source electrode is connected with the data line, the drain electrode is connected with the pixel electrode;
• a passivation layer is formed on the source electrode, the drain electrode and the data line, and a via hole is formed in the passivation layer over the drain electrode;
• the pixel electrode of “” shape is formed on the passivation layer and connected with the drain electrode through the via hole in the passivation layer;
• the data line is formed on the common electrode through an insulating layer;
• the method comprising the step of:
• forming the data line below the position corresponding to the boundary between the “/” portion and the “\” portion of the pixel electrode of “” shape.

A fringe field switching (FFS) liquid crystal display device, comprising:

• a color filter substrate and an array substrate confronting each other and a liquid crystal layer sandwiched between the color filter substrate and the array substrate, wherein the array substrate comprises:
• a base substrate;
• and
• a common electrode, a gate line, a data line, a thin film transistor (TFT), a passivation layer, and a pixel electrode of “” shape, which are all formed on the base substrate,
• wherein the TFT comprises a gate electrode, a source electrode and a drain electrode, the gate electrode is connected with the gate line, the source electrode is connected with the data line, and the drain electrode is connected with the pixel electrode;
• a passivation layer is formed on the source electrode, the drain electrode and the data line, and a via hole is formed in the passivation layer over the drain electrode;
• the pixel electrode of “” shape is formed on the passivation layer and connected with the drain electrode through the via hole in the passivation layer;
• and
• the data line is formed on the common electrode through an insulating layer and provided below the position corresponding to the boundary between the “/” portion and the “\” portion of the pixel electrode of “” shape.