Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorKoichiro Kamata
Life of this patent
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Abstract
A semiconductor device includes a semiconductor layer including a channel region, and a first region and a second region to which an impurity element is introduced to make the first region and the second region a source and a drain, a third region, and a gate electrode provided to partly overlap with the semiconductor layer with a gate insulating film interposed therebetween In the semiconductor layer, the first region is electrically connected to the gate electrode through a first electrode to which an AC signal is input, the second region is electrically connected to a capacitor element through a second electrode, the third region overlaps with the gate electrode and contains an impurity element at lower concentrations than each of the first region and the second region.
Claims30
A semiconductor device comprising:
- a semiconductor comprising:
- a first region comprising an impurity element imparting n-type conductivity;
- a second region comprising the impurity element imparting n-type conductivity;
- a third region between the first region and the second region;
- and
- a channel region between the first region and the third region;
- and
- a gate electrode overlapped with the semiconductor with a gate insulating film interposed between the gate electrode and the semiconductor,
- wherein the first region is electrically connected to the gate electrode through a first electrode,
- wherein the second region is electrically connected to an electrode of a capacitor element through a second electrode,
- wherein the channel region overlaps with the gate electrode and is in contact with the first region,
- wherein the third region overlaps with the gate electrode, and
- wherein the third region comprises the impurity element at lower concentrations than each of the first region and the second region.
A semiconductor device comprising:
- an antenna circuit;
- a rectifier circuit operationally connected to the antenna circuit and comprising a transistor comprising:
- a semiconductor comprising:
- a first region comprising an impurity element imparting n-type conductivity;
- a second region comprising the impurity element imparting n-type conductivity;
- a third region between the first region and the second region;
- and
- a channel region between the first region and the third region;
- a gate electrode overlapped with the semiconductor with a gate insulating film interposed between the gate electrode and the semiconductor;
- a constant voltage circuit electrically connected to the rectifier circuit;
- and
- a logic circuit electrically connected to the constant voltage circuit,
- wherein the first region is electrically connected to the gate electrode through a first electrode,
- wherein the second region is electrically connected to an electrode of a capacitor element through a second electrode,
- wherein the channel region overlaps with the gate electrode and is in contact with the first region, and
- wherein the third region overlaps with the gate electrode, and
- wherein the third region comprises the impurity element at lower concentrations than each of the first region and the second region.
A semiconductor device comprising:
- a semiconductor comprising:
- a first region comprising an impurity element imparting n-type conductivity;
- a second region comprising the impurity element imparting n-type conductivity;
- a third region comprising an impurity element imparting n-type conductivity between the first region and the second region;
- a fourth region between the first region and the third region;
- a fifth region between the second region and the third region;
- a first channel region between the first region and the fourth region;
- and
- a second channel region between the second region and the fifth region;
- a first gate electrode overlapped with the first channel region and the fourth region with a gate insulating film interposed between the first gate electrode and the semiconductor;
- and
- a second gate electrode overlapped with the second channel region and the fifth region with the gate insulating film interposed between the second gate electrode and the semiconductor,
- wherein the first region and the second region are electrically connected to the first gate electrode and the second gate electrode through a first electrode and a second electrode, respectively,
- wherein the third region is electrically connected to an electrode of a capacitor element through a third electrode,
- wherein the first channel region is in contact with the first region,
- wherein the second channel region is in contact with the second region,
- wherein the fourth region comprises the impurity element at lower concentrations than each of the first region and the second region, and
- wherein the fifth region comprises the impurity element at lower concentrations than each of the first region and the second region.
Dependencies are inferred from the claim text.