Solid-state image sensor having a voltage applier and signal readout method thereof
AssigneeNational University Corporation Nara Institute of Science and Technology
InventorsKeiichiro Kagawa, Jun Ohta
Life of this patent
Estimating the term…
Loading patent…
AssigneeNational University Corporation Nara Institute of Science and Technology
InventorsKeiichiro Kagawa, Jun Ohta
Estimating the term…
After resetting the potential VPD of the photodiode (11) to the predetermined potential VRST, light is incident onto the photodiode (11) for a predetermined period to decrease the VPD corresponding to the amount of the incident light. After that, a declivous ramp voltage VRAMP is applied to the source terminal of the first MOS transistor (12) which is a common-source amplifier for reading out the VPD. When the voltage difference between the gate and source of the MOS transistor (12) exceeds a threshold voltage, the MOS transistor is turned on and the output suddenly decreases. If a signal having a pulse width from the starting point of the sweep of the ramp voltage to the sudden lowering point of the output is generated, the pulse width depends on the amount of the incident light. With the signal readout of this PWM method, it is possible to lower the power consumption while a wide dynamic range is maintained, and to downsize the picture cells to achieve a higher number of picture cells.
A solid-state image sensor comprising:
A signal readout method of a solid-state image sensor comprising:
A solid-state image sensor comprising:
A signal readout method of a solid-state image sensor comprising:
Dependencies are inferred from the claim text.