Method for stacking serially-connected integrated circuits and multi-chip device made from same

A method of fabricating a multi-chip device having two pairs of stacked chips, comprising:

• flipping a first chip so that its top side bearing transistors faces in a first direction to become a bottom chip;
• placing a second chip on top of the flipped first chip, the second chip being substantially identical in pad arrangement and placement to the first chip;
• creating through pad and chip via holes to facilitate connection of signal pads of the top chip to corresponding signal pads of the bottom chip to create at least one series connection and at least one parallel connection;
• disposing an insulation layer in the via holes;
• and
• disposing a conductor in the via holes to create through-via connections between the pads on the top chip and the bottom chip to create a stacked pair of integrated circuit chips;
• depositing an insulation layer on top of the stacked pair of integrated circuit chips;
• forming contact holes in the insulation layer to permit connection between certain adjacent signal pads when another chip is later placed on top;
• depositing a conductor into the contact holes;
• etching a conductor layer to remove excess conductor material from the portions outside the contact holes;
• attaching two previously combined chips on top of the stacked pair of integrated circuit chips to create a multi-chip circuit for a multi-chip package, the two previously combined chips being substantially identical to the stacked pair of integrated circuit chips;
• and
• adding wire bonding to connect input signal pads of the top chip to an output side of a controller and to connect output signal pads from the bottom chip to an input side of the controller;
• and
• covering the entire package or compound.