Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon

A method of forming an integrated circuit device, comprising:

• forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions, on a semiconductor substrate;
• depositing a mask layer to expose at least a portion of the sacrificial spacer on the semiconductor substrate;
• removing the sacrificial spacer by selectively etching the exposed sacrificial spacer using the mask layer as an etchin mask;
• and
• forming a stress-inducing electrically insulating layer that is configured to induce a net tensile or compressive stress in a channel region of the field effect transistor, on the sidewall of the gate electrode;
• wherein the silicided source/drain regions comprise source/drain regions having a first metal silicide layer thereon that is self-aligned to the sacrificial spacer;
• wherein depositing a mask layer comprises:
• forming a mask layer on the field effect transistor;
• and
• partially etching back the mask layer to expose the sacrificial spacer;
• wherein the field effect transistor comprises a second metal silicide layer on the gate electrode;
• wherein partially etching comprises partially etching back the mask layer to expose the sacrificial spacer and the second metal silicide layer;
• and
• wherein selectively etching comprises exposing the second metal silicide layer to a wet and/or dry etchant.

A method of forming an integrated circuit device, comprising:

• forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions, on a semiconductor substrate;
• depositing a mask layer to expose at least a portion of the sacrificial spacer on the semiconductor substrate;
• removing the sacrificial spacer by selectively etching the exposed sacrificial spacer using the mask layer as an etching mask;
• and
• forming a stress-inducing electrically insulating layer that is configured to induce a net tensile or compressive stress in a channel region of the field effect transistor, on the sidewall of the gate electrode;
• wherein the silicided source/drain regions comprise source/drain regions having a first metal silicide layer thereon that is self-aligned to the sacrificial spacer;
• wherein depositing a mask layer comprises:
• forming a mask layer on the field effect transistor;
• partially etching back the mask layer to expose the sacrificial spacer;
• and
• removing the partially etched-back mask layer;
• and
• wherein forming a stress-inducing electrically insulating layer comprises depositing a stress-inducing electrically insulating layer on an upper surface and the sidewall of the gate electrode.

A method of forming an integrated circuit device, comprising:

• forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and LDD source/drain regions, on a semiconductor substrate;
• and
• replacing the sacrificial spacer with a stress-inducing electrically insulating layer that is configured to induce a net tensile or compressive stress in a channel region of the field effect transistor;
• wherein the LDD source/drain regions have silicided layers thereon;
• and
• wherein replacing the sacrificial spacer comprises selectively etching the sacrificial spacer using a mask layer to protect the silicided layers from etching damage.