Reduction of sheet resistance of phosphorus implanted poly-silicon
AssigneeNXP B.V.
InventorsWolfgang Euen, Stephan Gross
Life of this patent
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Abstract
There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.
Claims11
In an MOS transistor structure, the structure having a gate region, drain region and source region, a method for reducing the sheet resistance of the gate region, the method comprising:
- depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region;
- implanting amorphizing species at a first predetermined dose into the intrinsic amorphous silicon in the gate region;
- and
- implanting phosphorus species into the gate region at a second predetermined dose.
A method of forming a MOS integrated circuit comprising:
- forming a gate oxide on a substrate;
- depositing amorphous silicon on the gate oxide at a predetermined temperature;
- amorphizing the amorphous silicon with an Ar+ implant at a predetermined dose;
- implanting phosphorus another predetermined dose into the amorphous silicon;
- and
- patterning the amorphous silicon to define a gate region.
Dependencies are inferred from the claim text.