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US 7,923,338 B2Granted
Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence
AssigneeGlobalfoundries Inc.
InventorsMaciej Wiatr, Roman Boschke, Anthony Mowry
Life of this patent
Estimating the term…
Abstract
By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.
Claims24
A method, comprising:
- forming a spacer element comprising an etch stop layer portion and a spacer layer portion at sidewalls of a gate electrode structure of a transistor by forming an etch stop layer and a spacer layer and performing an anisotropic etch process using said etch stop layer as an etch stop;
- forming first drain and source areas of drain and source regions of said transistor by using said sidewall spacer element as a first implantation mask;
- reducing a width of said spacer element to a first reduced width by removing only a first portion of said spacer layer portion of said spacer element;
- and
- forming an intermediate portion of said drain and source regions by using the spacer element with said first reduced width as a second implantation mask.
2 more elements
A method, comprising:
- forming a spacer layer having a substantially homogenous material composition above a transistor;
- etching said spacer layer to form a sidewall spacer element at a sidewall of a gate electrode structure of said transistor, wherein said sidewall spacer element comprises a first portion and a second portion, said first and second portions each comprising material of said spacer layer;
- performing a first implantation process to form a first portion of drain and source regions of said transistor;
- reducing a width of said sidewall spacer element by removing only said first portion of said sidewall spacer element and leaving said second portion;
- and
- after reducing said width, performing a second implantation process to form a second portion of said drain and source regions of said transistor.
3 more elements
A method, comprising:
- determining a first target width of a spacer element for defining deep drain and source regions of a specified type of transistor;
- determining a second target width of a spacer element for defining intermediate drain and source regions of said specified type of transistor;
- forming an etch stop layer above one or more substrates, each of said one or more substrates including said specified type of transistor;
- forming a spacer layer on said etch stop layer on the basis of said first target width;
- etching said spacer layer to form said spacer element by using said etch stop layer as an etch stop, said spacer element comprising an etch stop layer portion and a spacer layer portion;
- forming said deep drain and source regions;
- reducing a width of said spacer element on the basis of said second target width by removing only a first portion of said spacer layer portion of said spacer element;
- and
- forming said intermediate drain and source regions.
6 more elements
Dependencies are inferred from the claim text.