Method of fabricating recess channel transistor having locally thick dielectrics and related devices
AssigneeSamsung Electronics Co., Ltd.
InventorsSung-Hee Han, Jin-Woo Lee, Tae-Young Chung, Ja-Young Lee
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AssigneeSamsung Electronics Co., Ltd.
InventorsSung-Hee Han, Jin-Woo Lee, Tae-Young Chung, Ja-Young Lee
Estimating the term…
Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.
A method of fabricating a recess channel transistor, comprising:
A method of fabricating a recess channel transistor, comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.
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This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0091733, filed Sep. 10, 2007, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.
1. Field
Example embodiments relate to a semiconductor device and a method of fabricating the same, and more particularly, to a method of fabricating a recess channel transistor having locally thick dielectrics and a related device.
Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1-11 represent non-limiting, example embodiments as described herein.
FIGS. 1 to 11 are cross-sectional views illustrating a method of fabricating a semiconductor device according to example embodiments.
It should be noted that these Figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.
Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments may, however, be embodied in different forms and should not be construed as limited to example embodiments set forth herein. Rather, example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. In addition, when a layer is described to be formed on another layer or on a substrate, this means that the layer may be formed on the other layer or on the substrate, or a third layer may be interposed between the layer and the other layer or the substrate. Like numbers refer to like elements throughout the specification.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Thermal treatments, e.g. annealing or sintering: for altering the shape of semiconductors, e.g. smoothing the surface
Of igfets: non-planar channels of IGFETs
Forming recessed gates, e.g. by using local oxidation: by etching at gate locations
Characterised by the conducting layers: characterised by their lengths or sectional shapes
About 2 years 2 months of term left · ends 7 Jan 2029 (estimated)