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AssigneeFreescale Semiconductor, Inc.
InventorsTed R. White, Brian A. Winstead
Estimating the term…
A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.
A method of forming a non-volatile memory cell comprising:
A method of forming a non-volatile memory cell comprising:
A method of forming a non-volatile memory cell comprising:
Dependencies are inferred from the claim text.
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Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
Nanotechnology for information processing, storage or transmission
Characterised by the shapes, relative sizes or dispositions of the floating gate electrode: having at least one additional gate other than the…
Of data-storage electrodes: comprising conductor-insulator-conductor-insulator-semiconductor structures
About 2 years 1 month of term left · ends 9 Dec 2028 (estimated)
1. Field
This disclosure relates generally to non-volatile memories (NVMs), and more specifically, to NVM cells with split gates.
2. Related Art
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
FIG. 1 is a semiconductor device at a stage in processing according to a first embodiment;
FIG. 2 is the semiconductor device of FIG. 1 at a subsequent stage in processing;
A split gate non-volatile memory cell provides increased endurance by reducing the electrical field at a corner of the control gate. This is achieved by increasing the radius of curvature of that corner. The effect then is that during erase there is less trap-up. Traps are locations in the dielectric under the control gate that can trap electrons. As more and more traps become filled with electrons, the difference between a programmed state and an erased state becomes less and thus becomes harder to detect. The increase in radius curvature results in reducing the field and thus avoids the corner region providing an inordinate contribution to trap-up.
The semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
Shown in FIG. 1 is a semiconductor device 10 comprising a semiconductor substrate 12, a gate dielectric 14 on semiconductor substrate 12, and a polysilicon layer 16 over gate dielectric 14. Gate dielectric 14 may be a grown oxide which is common for gate dielectrics and may be 2 nanometers in thickness. A high K dielectric may also be used and would likely have a different thickness. Polysilicon layer 16 may be 150 nanometers in this example but could be another thickness.