Method for gap filling in a gate last process

A method of fabricating a semiconductor device comprising:

• providing a semiconductor substrate having a first region and a second region;
• forming a first gate structure over the first region and a second gate structure over the second region, the first and second gate structures each including a high-k dielectric layer, a dummy poly gate, and a hard mask;
• forming a contact etch stop layer (CESL) over the first and second gate structures including the hard masks of the first and second gate structures, respectively;
• modifying a profile of the CESL, such that a gap measured between a first portion of the CESL, over the first gate structure and a second portion of the CESL over the second gate structure becomes larger;
• forming an interlayer dielectric (ILD) over the modified CESL substantially filling in the gap;
• performing a chemical mechanical polishing (CMP) on the ILD layer to remove the hard masks from the first and second gate structures, respectively, and expose the dummy poly gates of the first and second structures, respectively;
• and
• removing the dummy poly gates from the first and second gate structures, respectively, and replacing them with metal gate structures.

A method of fabricating a semiconductor device comprising:

• providing a semiconductor substrate;
• forming one or more gate structures over the semiconductor substrate;
• forming an etch stop layer over the semiconductor substrate, including over the one or more gate structures;
• modifying a profile of the etch stop layer;
• forming a dielectric layer over the modified etch stop layer;
• and
• performing a chemical mechanical polishing process on the dielectric layer until a top portion of the one or more gate structures is reached.