Methods of fabricating vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors

A method of fabricating a silicon carbide metal-oxide semiconductor field effect transistor, comprising the steps of:

• providing a drift layer of n-type silicon carbide;
• providing first regions of p-type silicon carbide adjacent the drift layer;
• providing a first region of n-type silicon carbide between peripheral edges of the first regions of p-type silicon carbide;
• providing second regions of n-type silicon carbide in the first regions of p-type silicon carbide, wherein the second regions of n-type silicon carbide have a carrier concentration greater than a carrier concentration of the drift layer and are spaced apart from the peripheral edges of the first regions of p-type silicon carbide;
• providing an oxide layer on the drift layer, the first region of n-type silicon carbide and the second regions of n-type silicon carbide;
• and
• providing third regions of n-type silicon carbide laterally extending along respective floors of the first regions of p-type silicon carbide and between the first regions of p-type silicon carbide and the drift layer, wherein the first and third regions of n-type silicon carbide define an n-type limiting region having a carrier concentration greater than the carrier concentration of the drift layer, wherein the first region of n-type silicon carbide has a higher carrier concentration than a carrier concentration of the drift layer and has a lower carrier concentration than the carrier concentration of the third regions of n-type silicon carbide;
• providing source contacts on portions of the second regions of n-type silicon carbide;
• providing a gate contact on the oxide layer;
• and
• providing a drain contact on the drift layer opposite the oxide layer.

A method of fabricating a silicon carbide metal-oxide semiconductor field effect transistor comprising:

• providing an n-type silicon carbide drift layer;
• providing spaced apart p-type silicon carbide well regions;
• and
• providing an n-type silicon carbide limiting region between the well regions and the drift layer, wherein the n-type limiting region comprises a first portion laterally extending along respective floors of the well regions and a second portion adjacent to respective sidewalls of the well regions,
• wherein the n-type limiting region has a carrier concentration higher than a carrier concentration of the drift layer, and wherein the first portion has a carrier concentration higher than a carrier concentration of the second portion.