Manufacturing method for planar independent-gate or gate-all-around transistors

A method for fabricating a planar gate-all-around FET on a bulk semiconductor substrate, the method comprising:

• a) providing a substrate with an active semiconductor region laterally defined by an isolation region, with a sacrificial layer buried under a semiconductor layer and with a surface sacrificial layer;
• b) depositing a hard mask layer;
• c) patterning the hard mask layer in a stripe shape so as to cause the hard mask layer to extend, in a channel direction pointing along the longitudinal direction of the FET channels, not only in the active semiconductor region but also on a part of the isolation region;
• d) fabricating source and drain regions;
• e) fabricating a recess in the isolation region so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that provides a lateral access for an etching agent to the buried sacrificial layer and so as to let the recess undercut portions of the hard mask layer in the channel direction;
• f) removing the buried sacrificial layer and the surface sacrificial layer, thus forming tunnels with semiconductor tunnel walls in place of the buried and surface sacrificial layers;
• g) depositing a gate stack comprising a dielectric layer and a gate layer in the recess and on the semiconductor tunnel walls, thus completing a gate stack;
• and
• h) trimming the gate stack.

A method for fabricating a planar independent-double-gate FET and a planar gate-all-around FET on a bulk semiconductor substrate, comprising:

• fabricating the planar independent-double gate-FET according to a method, comprising,
• 1a) providing a substrate-with an active semiconductor region-laterally defined by an isolation region and with a sacrificial layer-buried under a semiconductor layer;
• 1b) depositing a first gate-dielectric layer-and a first gate layer, and depositing a hard mask layer on the first gate layer;
• 1c) laterally trimming the first gate-dielectric layer and the first gate layer in a stripe shape so as to cause them to extend, in a channel direction-pointing along the longitudinal direction of the FET channels, not only in the active semiconductor region-but also on portions of the isolation region;
• 1d) fabricating source and drain regions;
• 1e) fabricating a recess in the isolation region so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that provides a lateral access for an etching agent to the buried sacrificial layer and so as to cause the recess to undercut portions of the first gate stack in the channel direction;
• 1f) selectively removing the buried sacrificial layer with the etching agent, thus forming a tunnel with semiconductor tunnel walls in place of the buried sacrificial layer;
• 1g) depositing a second dielectric layer and a second gate layer in the recess and on the semiconductor tunnel walls, thus completing a gate-stack;
• 1h) laterally trimming the gate stack so as to separate top and bottom gate layers;
• and
• fabricating the planer gate-all-around FET according to a method comprising,
• 2a) providing a substrate-with an active semiconductor region -laterally defined by an isolation region, with a sacrificial layer buried under a semiconductor layer and with a surface sacrificial layer;
• 2b) depositing a hard mask layer;
• 2c) patterning the hard mask layer in a stripe shape so as to cause the hard mask layer to extend, in a channel direction pointing along the longitudinal direction of the FET channels, not only in the active semiconductor region but also on a part of the isolation region;
• 2d) fabricating source and drain regions;
• 2e) fabricating a recess in the isolation region so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that provides a lateral access for an etching agent to the buried sacrificial layer and so as to let the recess undercut portions of the hard mask layer in the channel direction;
• 2f) removing the buried sacrificial layer-and the surface sacrificial layer, thus forming tunnels with semiconductor tunnel walls in place of the buried and surface sacrificial layers;
• 2g) depositing a gate stack comprising a dielectric layer and a gate layer in the recess and on the semiconductor tunnel walls, thus completing a gate stack;
• and
• 2h) trimming the gate stack.