Method for manufacturing a semiconductor package
AssigneeShinko Electric Industries Co., Ltd.
InventorsKeisuke Ueda, Takaharu Miyamoto, Ryuichi Matsuki
Life of this patent
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Abstract
A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.
Claims12
A method for manufacturing a semiconductor package, the method comprising;
- (a) arranging a plurality of low thermal expansion material plates with clearances provided therebetween in a grid pattern in a plane;
- (b) providing resin layers in the clearances, thereby forming an integral underlying plate comprising a plurality of underlying plates, wherein each of the underlying plates comprises:
- a corresponding one of the low thermal expansion material plates;
- and the resin layer surrounding the corresponding one of the low thermal expansion material plates;
- (c) forming a build-up wiring layer comprising a plurality of metal wiring layers and a plurality of insulation resin layers, on the integral underlying plate, thereby obtaining a semiconductor package collective plate comprising a plurality of semiconductor packages, wherein each of the semiconductor package comprises:
- a corresponding one of the underlying plates;
- and a corresponding portion of build-up wiring layer formed on the corresponding one of the underlying plates;
- and
- (d) cutting portions of the semiconductor package collective plate where the resin layers are provided, thereby dividing the semiconductor package collective plate into the plurality of semiconductor packages.
A method for manufacturing a semiconductor package, the method comprising:
- (a) arranging a plurality of low thermal expansion material plates with clearances provided therebetween in a grid pattern in a plane;
- (b) providing resin layers in the clearances, thereby forming an integral underlying plate comprising a plurality of underlying plates, wherein each of the underlying plates comprises:
- a corresponding one of the low thermal expansion material plates;
- and the resin layer surrounding the corresponding one of the low thermal expansion material plates;
- (c) stacking the two integral underlying plates on each other, thereby obtaining an integral multilayered plate;
- (d) forming build-up wiring layers comprising a plurality of metal wiring layers and a plurality of insulation resin layers, on both surfaces of the integral multilayered plate;
- (e) after step (d), dividing the integral multilayered plate into the two integral underlying plates on which each of the built-up wiring layers is formed, thereby obtaining two semiconductor package collective plates each comprising a plurality of semiconductor packages, wherein each of the semiconductor packages comprises:
- a corresponding one of the underlying plates;
- and a corresponding portion of build-up wiring layer formed on the corresponding one of the underlying plates;
- and
- (f) cutting portions of the semiconductor package collective plates where the resin layers are provided, thereby dividing the semiconductor package collective plates into the plurality of semiconductor packages.
Dependencies are inferred from the claim text.