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US 7,922,920 B2Granted
Systems, methods, and apparatus of a low conductance silicon micro-leak for mass spectrometer inlet
AssigneeThe United States of America as represented by the Administrator of the National Aeronautics and Space Administration
InventorsDan N. Harpold, Hasso B. Niemann, Brian G. Jamieson, Bernard A. Lynch
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Abstract
Systems, methods and apparatus are provided through which in some embodiments a mass spectrometer micro-leak includes a number of channels fabricated by semiconductor processing tools and that includes a number of inlet holes that provide access to the channels.
Claims15
A method to fabricate at least one micro-leak structure, the method comprising:
- fabricating channels in the at least one micro-leak structure by a plurality of semiconductor processing tools;
- mounting the at least one micro-leak structure in an inlet of a tube of a gaseous sampling device;
- patterning two double-sided polished silicon wafers with alignment marks from standard photolithography techniques;
- transferring a contact aligner and alignment marks to the silicon in a plasma etch:
- aligning inlet holes on one of the double-sided polished silicon wafers micro-channels on the other double-sided polished silicon wafer;
- removing photoresist from the two double-sided polished silicon wafers;
- removing patterned oxide layers from the first of the two double-sided polished silicon wafers in a dilute hydrofluoric acid solution to leave a smoother silicon surface that can interfere with the bonding surface of the wafer;
- bonding the two double-sided polished silicon wafers in a wafer bonder;
- annealing the two double-sided polished silicon wafers into a thermal oxidation tube;
- patterning into one side of the bonded wafer pair inlet holes and circular dicing lanes to define the final device diameter;
- etching holes and dicing lanes through to the center of the wafer pair;
- and
- etching matching dicing lanes and a single outlet hole on the opposite side of the wafer pair.
10 more elements
A method to fabricate at least one micro-leak structure, the method comprising:
- fabricating channels in the at least one micro-leak structure by a plurality of semiconductor processing tools;
- mounting the at least one micro-teak structure in an inlet of a tube of a gaseous sampling device;
- patterning a surface of a first substrate with photolithography, and
- etching a pattern into the surface of the first substrate, the etched pattern comprising one or more channels operable to flow gas;
- patterning the first substrate with photolithography resulting in a pattern of inlet holes;
- etching inlet holes of the pattern through the first substrate, the inlet holes being operable to introduce gas to the micro-leak channels;
- patterning a surface of a second substrate with photolithography, and
- etching inlet holes of the pattern through the second substrate, the inlet holes being operable to introduce gas to the micro-leak channels on the opposite side of the second substrate;
- aligning the second substrate to the first substrate into a stack;
- and
- bonding the second substrate to the first substrate using a direct bonding process to seal the channels on the inside of the two-substrate stack, and thus produce a gas flow device in which the gas is introduced to one or more micro-leak channels through the inlet holes fabricated into the silicon or other substrate, caused to flow through the conductance limiting channels, and exit through the outlet holes on the other side, wherein the bonding process further comprises a bonding process selected from the group of wafer bonding process consisting of anodic bonding process, fusion bonding process and eutectic bonding process.
8 more elements
Dependencies are inferred from the claim text.