Integrated circuits having a contact region and methods for manufacturing the same

An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:

• a fin structure, comprising:
• a first memory cell structure having at least one first active region of at least one first memory cell;
• a second memory cell structure having at least one second active region of at least one second memory cell, wherein the second memory cell structure is disposed above the first memory cell structure;
• a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, wherein the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure;
• and
• wherein the first step and the second step each comprise a first doped region doped with doping atoms of a first conductivity type, wherein the memory cell contact structure further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped region in a first direction.

An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:

• a substrate;
• a fin structure disposed above the substrate, the fin structure comprising:
• a memory cell region comprising a plurality of memory cell structures being disposed above one another, each memory cell structure comprising an active region of a respective memory cell;
• and
• a memory cell contacting region configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region comprises a plurality of contact regions which are at least partially displaced with respect to each other in a direction parallel to a main processing surface of the substrate;
• and
• wherein each of the plurality of contact regions comprises a first doped region doped with doping atoms of a first conductivity type, wherein each of the plurality of contact regions further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped region in a first direction.

A method for manufacturing an integrated circuit comprising a memory cell arrangement, the method comprising:

• forming a fin structure;
• forming a memory cell region in the fin structure, the memory cell region comprising a plurality of memory cell structures disposed above one another, each memory cell structure comprising an active region of a respective memory cell;
• and
• forming a memory cell contacting region configured to electrically contact each of the memory cell structures, such that the memory cell contacting region comprises a plurality of contact regions which are at least partially displaced with respect to each other in a direction parallel to a main processing surface of the substrate, wherein each of the plurality of contact regions comprises a first doped region doped with doping atoms of a first conductivity type, wherein each of the plurality of contact regions further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped region in a first direction.